Flip-flop having improved synchronous reset

Details Flip-flop having improved synchronous reset Flip-flop having improved synchronous reset

1983-06-02

1986-03-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 307299A, H03K 3289

Patent

active

045785996

ABSTRACT:
A flip-flop is provided having a data gate circuit for receiving input data and generating therefrom first and second complementary internal data signals representative of the input data. A master circuit is coupled to the data gate circuit for receiving a clock pulse and for latching the internal data signals during a predetermined portion of the clock pulse. A slave circuit is coupled to the master circuit for storing the internal data signals. A reset circuit supplies a synchronous reset signal to the master circuit for resetting the first and second complementary internal data signals on the occurrence of the next clock pulse.

REFERENCES:
patent: 3622803 (1971-11-01), Cooper et al.
patent: 4289979 (1981-09-01), Muller
patent: 4349753 (1982-09-01), Scavuzzo
patent: 4491745 (1985-01-01), Birch
patent: 4506165 (1985-03-01), Gulati et al.
patent: 4517475 (1985-05-01), Petty
Wu, W. W. Master-Slave Flip-Flop, IBM Technical Disclosure Bulletin, vol. 16, No. 7, Dec. 1973, pp. 2131-2132.

Affiliated with

Also associated with

Rating

Flip-flop having improved synchronous reset does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flip-flop having improved synchronous reset, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-flop having improved synchronous reset will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-633069