Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-01-28
2001-03-06
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S199000, C327S203000
Reexamination Certificate
active
06198323
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrical circuits, and, in particular, to edge-triggered flip-flops, such as master-slave flip-flops, and level-sense flip-flops, often called latches.
2. Description of the Related Art
A master-slave flip-flop is an electrical device that temporarily stores data, where the data is transferred into and within the device on the edges of clocking signals. The master stage of such a flip-flop stores data received at an input port D during one phase of a two-phase clock. On the opposite phase of the two-phase clock, the slave stage stores the data received from the master stage and presents that stored data at an output port Q of the master-slave flip-flop.
FIG. 1
shows a schematic drawing of a prior-art implementation of a static master-slave flip-flop
100
that relies on switched feedback techniques to retain data. Flip-flop
100
comprises four switches S
1
-S
4
and four drivers D
1
-D
4
(implemented using inverters INV
1
-INV
4
, respectively) arranged and operated to move data through flip-flop
100
in a particular manner. Flip-flop
100
has a master stage, consisting of switches S
1
and S
2
and inverters INV
1
and INV
2
, and a slave stage, consisting of switches S
3
and S
4
and inverters INV
3
and INV
4
.
The master and slave sections of flip-flop
100
each provide memory. This is achieved by feeding back a signal from the output of each stage to its input, thereby holding the output at its present value. If the driver in each stage is inverting, then the feedback path in each stage must also be inverting to provide this memory property.
Switches S
1
-S
4
are controlled by the levels of a two-phase clock, such that switches S
1
and S
4
are opened when switches S
2
and S
3
are closed, and vice versa. When switches S
1
and S
4
are closed and switches S
2
and S
3
are open, the master stage receives a data signal from input node D. When switches S
1
and S
4
are open and switches S
2
and S
3
are closed, data stored in the master stage is passed to the slave stage and output Q. When switches S
1
and S
4
are closed again and switches S
2
and S
3
are opened again, the data received by the slave stage from the master stage is stored in the slave stage and held at output Q, while the master stage receives a new data signal at input D. In this way, master-slave flip-flop
100
temporarily stores data received from an input data stream.
As described, with switch S
2
closed and switch S
1
open, the master stage of flip-flop
100
functions as a memory element. Switches S
1
and S
2
are typically transmission gates. The classic CMOS transmission gate is constructed of an N channel transistor and a P channel transistor, where the sources of these two devices are tied together and the drains of these devices are also tied together. When the P and N devices are both on, a low resistance path from source to drain is achieved. Alternately, if the P and N devices are turned off, the switch is considered open. Such a transmission gate is a non-inverting structure.
Flip-flops such as flip-flop
100
of
FIG. 1
have certain disadvantages. In particular, the most basic design requires four switches and four inverters, which utilize substantial layout area as well as power.
FIG. 2
shows a schematic drawing of a prior-art implementation of a static master-slave flip-flop
200
that relies on weak feedback techniques to retain data. In flip-flop
200
, inverters INV
2
and INV
4
are weak inverters that are designed to have a very small drive. As such, inverter INV
2
can be overdriven easily when switch S
1
is closed, and inverter INV
4
can be overdriven easily when switch S
3
is closed, but inverters INV
2
and INV
4
will provide enough positive feedback during standby (i.e., when switches S
1
and S
3
, respectively, are opened) to retain information in the flip-flop. Because inverters INV
2
and INV
4
have very small drives, flip-flop
200
can be designed without switches (such as switches S
2
and S
4
of
FIG. 1
) in the feedback paths of the master and slave stages, since the input signals received at nodes I
1
and I
3
from nodes D and
12
, respectively, will be sufficiently large to control the state of inverters INV
1
and INV
3
, no matter what signals are received from weak inverters INV
2
and INV
4
, respectively.
Flip-flop
200
has certain advantages over flip-flop
100
of FIG.
1
. First of all, flip-flop
200
has two fewer switches than flip-flop
100
. Moreover, flip-flop
200
replaces two of the strong inverters of flip-flop
100
with two weak inverters. As such, flip-flop
200
can be implemented with a smaller layout area.
Another desirable goal (in addition to smaller area) in designing flip-flops is to keep both setup time and clock-to-Q propagation time as short as possible. Setup time refers to the time that it takes to charge the master stage of the flip-flop. Analogously, clock-to-Q propagation time refers to the time that it takes to charge the slave stage of the flip-flop. Referring to
FIGS. 1 and 2
, setup time is the minimum amount of time that the input value D needs to be applied to the master stage before the master transmission gate S
1
is opened and still have the master stage retain the correct input value. Clock-to-Q propagation time is the amount of time between the clock edge that closes slave transmission gate S
3
and the correct data value reaching output Q.
It is often desirable to implement a flip-flop with preset and/or clear functionality. A preset condition configures the flip-flop to have an output value Q of 1, while a clear condition configures the flip-flop to have an output value Q of 0.
FIGS. 3-5
show three different prior-art implementations of static master-slave flip-flops having logic added to support both preset and clear functionality.
FIG. 3A
shows a static feedback flip-flop
300
with transmission gate switches in the master and slave feedback loops, similar to flip-flop
100
of FIG.
1
. In flip-flop
300
, drivers D
1
and D
4
are both implemented using a gate structure with OR and NAND gate functionality, with preset signal PD and clear signal CDN applied to those drivers to achieve the desired flip-flop preset and clear functionalities.
FIGS. 3B and 3C
show how the clock signal CKN and the preset signal PD are generated from the input clock signal CK and the input preset signal PDN, respectively.
Referring again to
FIG. 3A
, the setup time for flip-flop
300
is proportional to the capacitance at node i
1
. Similarly, the clock-to-Q propagation time for flip-flop
300
is proportional to the capacitance at node i
3
. In general, the lower the capacitances at nodes i
1
and i
3
, the lower the setup time and clock-to-Q propagation time, respectively. One of the disadvantages of the design of flip-flop
300
is that the implementation of driver D
1
as a relatively complex gate structure with applied preset and clear signals greatly increases the effective capacitance at node i
1
for a given drive capability of driver D
1
(as compared with using an inverter for driver D
1
), thereby greatly increasing the setup time for flip-flop
300
. Moreover, the use of gate structures for drivers D
1
and D
4
increases the layout size for flip-flop
300
, relative to a flip-flop implemented using simple inverters for drivers.
FIG. 4A
shows a static weak-keeper feedback flip-flop
400
, similar to flip-flop
200
of FIG.
2
. As was the case with flip-flop
200
, using weak keepers in the feedback paths of flip-flop
400
eliminates the need for feedback switches (e.g., switches S
2
and S
4
in
FIG. 1
) and allows all four drivers to be implemented using simple inverters, thereby decreasing the layout of flip-flop
400
relative to flip-flop
300
of FIG.
3
.
FIG. 4B
shows how the clock signals CKX and CKY are generated from the input clock signal CK, the input preset signal PDN, and the input clear signal CDN. Similarly,
FIGS. 4C and 4D
show how the clear signal CD and the preset signal PD ar
Lucent Technologies - Inc.
Mendelsohn Steve
Nguyen Hiep
Tran Toan
LandOfFree
Flip-flop having gated inverter feedback structure with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flip-flop having gated inverter feedback structure with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-flop having gated inverter feedback structure with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2532985