Flip-flop design and technique for scan chain diagnosis

Details Flip-flop design and technique for scan chain diagnosis Flip-flop design and technique for scan chain diagnosis

1997-01-28

1999-03-09

Tu, Trinh L.

Excavating

371 226, 324 731, 377 73, 377 75, G01R 3128

Patent

active

058810676

ABSTRACT:
A modification to conventional scan chain design is disclosed which can identify whether any connection in the scan chain is shorted to the supply voltage or ground (i.e., shorted to a logical 1 or logical 0) and the precise location of the short. Circuitry in the flip-flops (or other sequential elements) forming the scan chain allows the scan output of each flip-flop to be set or reset by switching a scan enable signal between logic states. If there is a fault in the scan chain where a node is stuck at a logical 1, then resetting the scan outputs of the flip-flops to 0 and clocking the flip-flops will result in a logical 1 being output from the last flip-flop after a number of clock pulses. The number of clock pulses indicates the position of the flip-flop in the scan chain which is associated with the fault. A similar technique detects a stuck-at-0 fault by setting the flip-flops to 1. In a preferred embodiment, each adjacent pair of flipflops in the chain consists of a flip-flop whose scan output can be reset to a 0 and a flip-flop whose scan output can be set to a 1.

REFERENCES:
patent: 4855669 (1989-08-01), Mahoney
patent: 5367551 (1994-11-01), Okumura et al.
patent: 5416784 (1995-05-01), Johnson
patent: 5574731 (1996-11-01), Qureshi
S. Edirisooriya and G. Edirisooriya, "Diagnosis of Scan Path Failures," Proceeding of 13th IEEE VLSI Test Symposium, Apr. 1995, Princeton, NJ pp. 250-255.
S. Kundu in Proceedings, "On Diagnosis of Faults in a Scan Chain," 11th IEEE VLSI Test Symposium, Apr. 1993, pp. 303-308.

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