Flip-flop controller for selectively disabling clock signal

Details Flip-flop controller for selectively disabling clock signal Flip-flop controller for selectively disabling clock signal

1996-01-23

1998-02-24

Nguyen, Hoa T.

Excavating

364556, G01R 3128

Patent

active

057217408

ABSTRACT:
A flip-flop controller including a clock controller for enabling or disabling a clock signal in response to a clock enabling signal and one or more flip-flops for selectively latching a function mode signal or scan test mode signal in response to a mode selection signal while being synchronous with the clock signal, is provided. As a result, a test vector is easily generated, fault coverage is increased to a desired degree using relatively few test vectors. Also, power consumption can be reduced by disabling the unnecessary portion of the clock signal applied to the flip-flop.

REFERENCES:
patent: 4463440 (1984-07-01), Nishiura et al.
patent: 5117443 (1992-05-01), Shires
patent: 5235600 (1993-08-01), Edwards
patent: 5467354 (1995-11-01), Yamauchi
patent: 5502689 (1996-03-01), Peterson et al.

Affiliated with

Also associated with

Rating

Flip-flop controller for selectively disabling clock signal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flip-flop controller for selectively disabling clock signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-flop controller for selectively disabling clock signal will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1879437