Flip-flop comprising two field effect transistors controllably c

Details Flip-flop comprising two field effect transistors controllably c Flip-flop comprising two field effect transistors controllably c

1978-05-24

1980-03-25

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307279, 307DIG3, 365205, 365208, H03K 520, H03K 3286, H03K 3353, G11C 706

Patent

active

041952391

ABSTRACT:
A flip-flop usable as a sense amplifier having two insulated-gate field effect transistors that may have different threshold voltages and that have gates connected to nodes of the flip-flop, sources connected in common, and drains connected to the nodes through a first and a second control transistor rendered conductive by first clock pulses and crosswise to the gates of the other field effect transistors through a third and a fourth control transistor turned on by second clock pulses appearing in substantial coincidence with disappearance of the respective ones of the first clock pulses. Capacitive loads charged to a precharge voltage are connected to the respective nodes. A source of a first activation voltage different from the precharge voltage by a value more than the higher of the threshold voltages is connected to the transistor sources during appearance of respective ones of the first clock pulses to change the precharged levels of the respective loads to such levels that are different from the first activation voltage by the respective threshold voltages. A variation is given to the precharge level of a selected load in substantial coincidence with appearance of a selected one of the second clock pulses. A source of a second activation voltage, such as ground, different from the precharge voltage by a value more than the difference between the first activation voltage and the precharge voltage is connected to the transistor sources after appearance of the selected one of the second clock pulses. An output signal related to the variation is obtained at the node connected to the selected load.

REFERENCES:
patent: 3588537 (1971-06-01), Brink
patent: 3868656 (1975-02-01), Stein et al.
patent: 3992704 (1976-11-01), Kantz
patent: 4000413 (1976-12-01), Wong et al.
patent: 4028557 (1977-06-01), Wilson
patent: 4122549 (1978-10-01), Kinoshita
patent: 4133049 (1979-01-01), Shirato
patent: 4138740 (1979-02-01), Itoh

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