Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-10-23
2003-01-21
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S218000, C327S219000
Reexamination Certificate
active
06509772
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to sequential circuits, and in particular to a flip-flop.
BACKGROUND OF THE INVENTION
Flip-flops have many uses in today's computers and digital circuits. Flip-flops are one of the most commonly used elements to implement sequential circuits, in which the primary output relies not only on the current values of the inputs, but also on the previous input values. A flip-flop is used to generate a steady state output signal having either a high (logical one) or a low (logical zero) potential.
A prior art flip-flop
100
is shown in FIG.
1
. Flip-flop
100
receives a clock signal CK and a data signal D to produce signals Q and Q*. Signals CK and D provide inputs to the gates of a stack of series-connected transistors, which include p-channel transistors P
1
and P
2
and n-channel transistors N
1
and N
2
. When the signal level of CK signal is low, P
1
and N
1
turn on, allowing signal D to propagate to node Y. Node Y connects to a transmission gate TG. When the signal level at CK signal is high, TG turns on, allowing the signal at node Y to pass to node L and subsequently become output signal Q and Q*.
One problem involved with flip-flop
100
is the speed of data signal D propagating to node Y when signal D is at a high level, because note Y has to be precharged through the series-connected transistors P
1
and P
2
. Another problem associated with flip-flop
100
includes an issue of charge sharing, which occurs when transistor P
1
and N
1
are off. When P
1
and N
1
are off, if data signal D changes from a high level to a low level; this low level activates transistor P
2
, however, since P
1
is off, the charge stored at node PP is shared by node Y. The charge sharing, sometimes, introduces inefficiency to the operation of flip-flop
100
by slowing it.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved flip-flop which can operate faster and has no charge sharing issue.
REFERENCES:
patent: 3993916 (1976-11-01), Copeland, III et al.
patent: 4709173 (1987-11-01), Nishimichi et al.
patent: 5239206 (1993-08-01), Yanai
patent: 5257223 (1993-10-01), Dervisoglu
patent: 5576645 (1996-11-01), Farwell
patent: 5619157 (1997-04-01), Kumata et al.
patent: 5774005 (1998-06-01), Partovi et al.
patent: 5831462 (1998-11-01), Witt et al.
Chen Zhanping
Ye Yibin
Cunningham Terry D.
Nguyen Long
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Flip-flop circuit with transmission-gate sampling does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flip-flop circuit with transmission-gate sampling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-flop circuit with transmission-gate sampling will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3047639