Flip-flop circuit with reduced power consumption

Details Flip-flop circuit with reduced power consumption Flip-flop circuit with reduced power consumption

2005-03-08

2005-03-08

Tan, Vibol (Department: 2819)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S210000, C327S099000, C326S093000, C326S095000

Reexamination Certificate

active

06864732

ABSTRACT:
A low power flip-flop is disclosed. The number of transistors which are coupled to the clock signal is reduced by more than half when compared with known flip-flop designs. The flip-flop comprises a pair of clocked transistors forming a pass gate and a plurality of inverters coupled thereto. By reducing the number of clock signal connections needed for reliable operation, the present invention reduces the power consumed by the flip-flop when operating at typical levels of activity by up to 70%.

REFERENCES:
patent: 5570051 (1996-10-01), Chiang et al.
patent: 5612632 (1997-03-01), Mahant-Shetti et al.
patent: 5774005 (1998-06-01), Partovi et al.

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