Flip-flop circuit with decreased time required from take in of d

Details Flip-flop circuit with decreased time required from take in of d Flip-flop circuit with decreased time required from take in of d

1991-11-22

1993-04-06

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307264, 307279, 307291, H03K 3284, H03K 3286, H03K 329

Patent

active

052006492

ABSTRACT:
A high speed D-type flip-flop circuit comprises a data take-in circuit for taking in a data input at a timing synchronized with a clock input, a data hold circuit for holding a data output determined by the data input taken in by the data take-in circuit until the next data input take-in time, and a data output forced update circuit. When the data input is taken in, the output determined thereby is governed by the data output forced update circuit and updated thereby. Then, the signal determined by the data input is transferred to an output terminal through the data take-in circuit and the data hold circuit, and the data output is held until the next update time.

REFERENCES:
patent: 4314166 (1982-02-01), Bismarck
patent: 4450371 (1984-05-01), Bismarck
patent: 4656368 (1987-04-01), McCombs et al.
patent: 4982111 (1991-01-01), Nakaizumi

Affiliated with

Also associated with

Rating

Flip-flop circuit with decreased time required from take in of d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flip-flop circuit with decreased time required from take in of d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-flop circuit with decreased time required from take in of d will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-538952