Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-08-26
2001-03-20
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S211000, C327S212000, C327S291000
Reexamination Certificate
active
06204707
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a flip-flop circuit with clock signal control function, and a clock control circuit. More specifically, the invention relates to a flip-flop circuit having suppressed electric power consumption, and a clock control circuit for suppressing electric power consumption.
2. Description of the Prior Art
In order to operate a flip-flop circuit, it is required to input clock signals thereto. On the time average, most of logic circuits in an integrated circuit are not operated to be stopped. However, since clock signals always carry out transition in accordance with the operating frequency thereof, most of electric power consumption of the integrated circuit is occupied by that of the flip-flop circuit and a clock tree. An example of such a typical flip-flop circuit is shown in FIG.
14
. As can be seen from
FIG. 14
, signals of high and low levels are alternately inputted to a CP terminal serving as a clock signal input terminal, and the gate terminals of 12 transistors, which are half of all of 24 transistors constituting a flip-flop circuit
10
, are charged and discharged whenever the signals are inputted.
A proposal to reduce electric power consumption of a flip-flop circuit is disclosed in Japanese Patent Laid-Open No.
4-298115.
In a circuit disclosed in Japanese Patent Laid-Open No.
4-298115,
a data input signal of a master slave flip-flop circuit is compared with a data output signal thereof. Only when the data input signal is different from the data output signal, a clock signal is supplied to the flip-flop circuit, and when the data input signal is the same as the data output signal, the level of a clock signal is fixed to be a low level.
However, in the construction disclosed in Japanese Patent Laid-Open No.
4-298115,
there is a problem in that malfunction occurs if the input signal of the flip-flop circuit varies while the clock signal remains at a high level. That is, it is assumed that the input signal to the flip-flop circuit varies when the supply of an internal clock signal to the flip-flop circuit is stopped, i.e., while the low level of the internal clock signal is held. In this case, if the level of a clock signal inputted from the outside is the high level, the level of the internal clock signal supplied to the flip-flop circuit varies from the low level to the high level, so that malfunction occurs.
In order to solve such a problem, Nogawa et al. has proposed a method for preventing malfunction by sufficiently shortening the time for a clock signal to remain at a high level (Symposium on VLSI Circuits Digest of Technical Paper, p101-102). If each of flip-flop circuits has a mechanism for generating a short-pule clock signal wherein the time for the clock signal to remain at the high level is sufficiently short, the area of the flip-flop circuit increases, and electric power consumption increases. Therefore, a plurality of flip-flop circuits are grouped, and short-pulse clock signals are collectively supplied to the group of flip-flop circuits. However, since a pulse-like signal has a great tendency to deteriorate when the signal propagates in a wiring, it is required to carefully design the distance between a clock signal generating circuit for generating such a short-pulse clock signal and a flip-flop circuit. It is also required to design the pulse width of the short-pulse clock signal in view of such an influence on distortion.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to prevent malfunction from occurring in a flip-flop circuit even if a data input signal to the flip-flop circuit varies in any timing, while suppressing electric power consumption. It is another object of the present invention to remove the need for adjusting the pulse width of a clock signal and to prevent the problem of distortion due to the propagation of the clock signal.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a flip-flop circuit with clock signal control function comprises: a data holding output circuit for receiving a data input signal and an internal clock signal and for holding a value of the data input signal in synchronism with the internal clock signal to output the value of the data input signal as a data output signal; a discord detecting circuit for receiving the data input signal and data output signal of the data holding output circuit and for detecting the discord of the data input signal with the data output signal to output a discord signal; and a clock control circuit for receiving an external clock signal and the discord signal, and for outputting a shorter pulse than one cycle of the external clock signal as the internal clock signal in synchronism with the rising or falling of the external clock signal when the data input signal discords with the data output signal, and a signal of a first level as the internal clock signal when the data input signal coincides with the data output signal.
According to another aspect of the present invention, there is provided a clock control circuit for receiving an external clock signal and a supply control signal and for outputting an internal clock signal, wherein the internal clock signal is an AND of a clock control signal and the external clock signal, the clock control signal being an AND of the supply control signal and a propagation control signal, and the propagation control signal being an OR of the clock control signal, and a NOT of the external clock signal.
REFERENCES:
patent: 5703513 (1997-12-01), Hashizume et al.
patent: 5999030 (1999-12-01), Inoue
patent: 04298115A (1992-10-01), None
patent: 8106786 (1996-04-01), None
Nogawa, et al., “A Data-Transition Look-Ahead DFF Circuit for Statistical reduction in Power Consumption,” 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 101-102.
Hamada Mototsugu
Kuroda Tadahiro
Hogan & Hartson LLP.
Kabushiki Kaisha Toshiba
Lam Tuan T.
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