Flip-flop circuit, scan path and storage circuit

Details Flip-flop circuit, scan path and storage circuit Flip-flop circuit, scan path and storage circuit

1996-09-05

1998-07-21

Canney, V.

Excavating

G06F 1106

Patent

active

057843848

ABSTRACT:
In order to obtain a flip-flop circuit which reduces an S/H time or a T-Q delay while suppressing power consumption, a master latch is formed by a dynamic half latch having a transmission gate (S1) and an invertor (INV1), while a slave latch is formed by a static half latch having transmission gates (S3, S4) and invertors (INV3, INV4). In the slave latch, the operation of the transmission gate (S4) is controlled not only by a clock signal (T) but by a mode signal (MODE). When the mode signal (MODE) is converted to a low level, the transmission gate (S4) enters a nonconducting state, so that the slave latch performs a dynamic operation.

REFERENCES:
Principles of CMOS VLSI Design, pp. 19-21 and 490-493, Neil H. E. Weste, et al.
Motorola, Semiconductor Technical Data, pages MPC27T416 1-15 and D, 1995, "16K x 16 Bit Cache-Tag Ram for PowerPC.TM. Processors".
IBM Technical Disclosure Bulletin, vol. 28, No. 8, pp. 3547-3548, 1986, "CMOS Toggle Flip-Flop".

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