Flip-flop circuit having transfer gate delay

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307481, 307279, 307594, 307269, H03K 513, H03K 19096, H03K 326

Patent

active

052647382

ABSTRACT:
The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by prolonging the transfer time for data from the master to the salve section of the flip-flop circuit.

REFERENCES:
patent: 4473760 (1984-09-01), Ambrosius, III et al.
patent: 4663546 (1987-05-01), Eitrheim et al.
patent: 4929850 (1990-05-01), Breuninger
patent: 5029279 (1991-07-01), Sasaki et al.
patent: 5107137 (1992-04-01), Kinugasa et al.
patent: 5132577 (1992-07-01), Ward

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