Flip-flop circuit having low standby power for driving synchrono

Details Flip-flop circuit having low standby power for driving synchrono Flip-flop circuit having low standby power for driving synchrono

1994-04-29

1996-03-05

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327199, 327208, 327215, H03K 3356

Patent

active

054971152

ABSTRACT:
A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory (SDRAM) including a complementary pair of data inputs for receiving data pulses, a clock input for receiving clock pulses, a capture latch circuit for capturing a bit, having a pair of complementary inputs and a pair of complementary outputs, apparatus for applying data pulses from the complementary data inputs to the inputs of the capture latch, apparatus for triggering the capture latch from the clock pulses, and apparatus for connecting the complementary outputs to each other through a bidirectional holding latch, whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs, and following the leading edge of a clock pulse and the one polarity of the data pulse the complementary outputs remain driven by the holding latch. The invention utilizes lower standby power in comparison to prior art flip-flop circuits.

REFERENCES:
patent: 4800296 (1989-01-01), Ovens et al.
patent: 4970406 (1990-11-01), Fitzpatrick et al.
patent: 4980577 (1990-12-01), Baxter
patent: 5049760 (1991-09-01), Ooms
patent: 5124568 (1992-06-01), Chen et al.
patent: 5281865 (1994-01-01), Yamashita et al.

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