Flip-flop circuit having low power data retention

Details Flip-flop circuit having low power data retention Flip-flop circuit having low power data retention

2006-10-17

2006-10-17

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000

Reexamination Certificate

active

07123068

ABSTRACT:
A flip-flop (10) has a normal mode and a low power mode to save power. The flip-flop (10) has a master latch (14) and a slave latch (20). The slave latch (20) is used to retain the condition of the flip-flop (10) during the low power mode, where power is withdrawn from the master latch (14) but maintained on the slave latch (20). The slave latch (20) may use transistors with lower leakage characteristics than the transistors that make up the master latch (14). These lower leakage characteristics may be achieved by a higher threshold voltage and/or a thicker gate dielectric. Operating speed of the flip-flop (10) is maintained by implementing the slave latch (20) so that no logic gate or switching transistor is in the critical timing path. Instead, the slave latch (20) has an input/output terminal to tap into the signal path between the master latch and an output circuit (22).

REFERENCES:
patent: 6492854 (2002-12-01), Ku
patent: 6870412 (2005-03-01), Cho
patent: 6873197 (2005-03-01), Kanba
patent: 2004/0090256 (2004-05-01), Cho

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