Flip-flop circuit having low power data retention

Details Flip-flop circuit having low power data retention Flip-flop circuit having low power data retention

2006-11-21

2006-11-21

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S218000

Reexamination Certificate

active

07138842

ABSTRACT:
A flip-flop (10) comprises a first latch circuit (18), a second latch circuit (24), and a third latch circuit (26). The first latch circuit (18) is coupled to receive a clock signal and a first power supply voltage. The second latch circuit (24) is coupled to the first latch circuit (18) and receives the clock signal and the first power supply voltage. Preparatory to entering a low power mode, the third latch circuit (26) receives a second power supply voltage and is coupled to the second latch circuit (24) in response to a power down signal. During the low power mode, the first power supply voltage is removed from the first and second latch circuits (18, 24). When returning to a normal operating mode, the first power supply voltage is provided to the first and second latch circuits (18, 24), and the third latch circuit (26) is coupled to the first latch circuit (18) in response to a power restore signal.

REFERENCES:
patent: 6492854 (2002-12-01), Ku
patent: 6870412 (2005-03-01), Cho
patent: 6873197 (2005-03-01), Kanba
patent: 2004/0075479 (2004-04-01), Gupta
patent: 2004/0090256 (2004-05-01), Cho

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