Flip-flop circuit

Details Flip-flop circuit Flip-flop circuit

1997-12-30

1999-12-07

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327211, 327212, 327258, H03K 3037, H03K 513

Patent

active

059990309

ABSTRACT:
A clock control circuit is provided in a flip-flop circuit, since a first clock signal supplied to a master latch circuit is generated by an OR logic between a reference clock signal and a skew adjustment clock signal, a second clock signal supplied to a slave latch circuit is generated in accordance with the reference clock signal, the first clock signal has a phase advanced from the second clock signal by exactly an amount of a skew margin. An input signal is fetched into the flip-flop circuit at the rising edge of the first clock signal, then is output at the rising edge of the second clock signal. By this, malfunction due to the clock skew is prevented. The flip-flop circuit can operate as in the normal mode by holding the skew adjustment clock at a logic "0".

REFERENCES:
patent: 5130568 (1992-07-01), Miller et al.
patent: 5175447 (1992-12-01), Kawasaki et al.
patent: 5619157 (1997-04-01), Kumata et al.

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