Flip-flop circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Reexamination Certificate

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Details

C327S218000, C327S200000, C326S095000, C326S098000

Reexamination Certificate

active

07345519

ABSTRACT:
A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that is shorter than the clock cycle, wherein only three N-type transistors are connected in series in the input section employing a dynamic circuit. A data signal is input directly to one of the three N-type transistors. On the other hand, a test input signal is input to an AND/OR inverter circuit. The AND/OR inverter circuit receives, as a control signal, the potential of the node obtained as the clock signal passes through two inverter circuits. Therefore, there is required only a short hold time for the test input signal.

REFERENCES:
patent: 5898330 (1999-04-01), Klass
patent: 5917355 (1999-06-01), Klass
patent: 5933038 (1999-08-01), Klass
patent: 6023179 (2000-02-01), Klass
patent: 6853228 (2005-02-01), Hirata et al.
patent: 2005/0151560 (2005-07-01), Hirata
patent: 2005/0283691 (2005-12-01), Chae
patent: 2004-159315 (2004-06-01), None
patent: 2005-210683 (2005-08-01), None
Klass ‘Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic’: Fabian Klass, Sun Microsystems Inc., 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 108, 109.

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