Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-07-31
2004-01-13
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000
Reexamination Certificate
active
06677795
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally a flip-flop circuit and more particularly to a flip-flop circuit of a master slave system that may have a reduced signal propagation delay period from switching a clock signal to providing an output signal so that high-speed operation may be improved.
BACKGROUND OF THE INVENTION
Recently, the operating frequency of even a CMOS (complementary metal oxide semiconductor) circuit can be required to be in the order of a GHz. In order to satisfy such a high frequency requirement, it has been necessary to improve the operating speed of a flip-flop circuit.
Referring now to
FIG. 9
, a circuit schematic diagram of a conventional flip-flop circuit is set forth and given the general reference character
900
.
Conventional flip-flop circuit
900
has a data input terminal
70
, a clock signal input terminal
71
and a data output terminal
72
. Conventional flip-flop circuit
900
includes clocked inverters (
75
,
76
, and
77
), inverters (
78
,
79
,
80
,
81
,
82
, and
83
), a p-channel data transfer gate
73
, and an n-channel data transfer gate
74
.
Data input terminal
70
is connected to an input of a clocked inverter
75
. Clocked inverter
75
has an output connected to an input terminal of inverter
78
. Inverter
78
has an output terminal connected to an input terminal of clocked inverter
76
and an input terminal of inverter
79
. Clocked inverter
76
has an output terminal connected to an input terminal of inverter
78
. Inverter
78
and clocked inverter
76
form a latch. Inverter
81
receives a clock signal at a clock signal input terminal
71
and provides an inverted clock signal CB as an input to inverter
82
. Inverter
82
provides a normal clock signal C.
Clocked inverter
75
receives the normal clock signal C at an inverted input terminal and inverted clock signal CB at a normal input terminal. Clocked inverter
76
receives the normal clock signal C at a normal input terminal and inverted clock signal CB at an inverted input terminal.
P-channel data transfer gate
73
has a source/drain terminal connected to an output of inverter
79
, another source/drain terminal connected to inputs of inverters (
80
and
83
), and a control gate connected to receive inverted clock signal CB. N-channel data transfer gate
74
has a source/drain terminal connected to an output of inverter
79
, another source/drain terminal connected to inputs of inverters (
80
and
83
), and a control gate connected to receive normal clock signal C.
Inverter
80
has a output connected to an input of clocked inverter
77
. Clocked inverter
77
has an output connected to inputs of inverters (
80
and
83
). Inverter
80
and clocked inverter
77
form a latch. Clocked inverter
77
receives inverted clock signal CB at a normal input terminal and normal clock signal C at an inverted input terminal.
Inverter
83
has an output connected to data output terminal
72
.
In conventional flip-flop circuit
900
, data from data input terminal
70
is latched in a latch (master latch) formed by inverter
78
and clocked inverter
76
by the rising edge of a clock signal received at clock signal input terminal
71
. At this time, p-channel data transfer gate
73
and n-channel data transfer gate
74
are also turned on (open) by the rising edge of a clock signal received at clock signal input terminal
71
. This data is then output at the data output terminal
72
by inverter
83
. Based on the falling edge of a clock signal received at clock signal input terminal
71
, p-channel data transfer gate
73
and n-channel data transfer gate
74
are also turned off (closed). At this time, clocked inverter
77
is enabled and the data is latched in the latch (slave latch) formed by inverter
80
and clocked inverter
77
.
Referring now to
FIG. 10
, a circuit schematic diagram of a flip-flop circuit is set forth and given the general reference character
1000
. Flip-Flop
1000
is proposed to eliminate or reduce a delay of inverters (
81
and
82
).
Flip-flop circuit
1000
includes the same constituents as conventional flip-flop circuit
900
. These same constituents are referred to by the same reference characters.
Flip-flop circuit
1000
differs from conventional flip-flop circuit
900
in that n-channel data transfer gate
74
has a control gate connected directly to the clock signal input terminal
71
. By doing so, a delay from the rising edge of a clock signal provided to clock signal input terminal
71
to data being output at data output terminal
72
can be improved by eliminating a delay of inverters (
81
and
82
) before turning on n-channel data transfer gate
74
. Otherwise, the structure of flip-flop circuit
1000
is identical to conventional flip-flop circuit
900
.
In conventional flip-flop circuit
900
, a timing at which n-channel data transfer gate
74
opens (is turned on) is delayed by a delay (T1+T2 as illustrated in
FIG. 2
which will be described later). The delay (T1+T2) corresponds to the propagation delay of inverters (
81
and
82
). This causes a delay in the change of data at data output terminal
72
with respect to a rising edge of a clock signal input at clock signal input terminal
71
.
In flip-flop circuit
1000
, a delay can be improved as compared to a delay in conventional flip-flop circuit
900
if a clock signal provided at clock signal input terminal
71
is ideal. However, the clock signal is typically rounded due to capacitance caused by, for example, wire routing or gate loads. The affect of the rounding of the clock signal waveform is illustrated in
FIGS. 4 and 5
.
FIG. 4
is a graph illustrating a relationship between rounding of rising edge of a clock signal waveform and a delay time of data switching from a high to a low logic level at an output of transfer gates.
FIG. 5
is a graph illustrating a relationship between rounding of a rising edge of a clock signal waveform and a delay time of data switching from a high to a low logic level at an output of transfer gates. Although the details will be described later, when the waveform of the rising edge of the clock signal waveform is rounded by less than about 1 nanosecond, the delay time in flip-flop circuit
1000
for data switching from a high to a low logic level is less than the delay time in conventional flip-flop circuit
900
. However, when the waveform of the rising edge of the clock signal waveform is rounded by more than about 1 nanosecond, the delay time in flip-flop circuit
1000
for data switching from a high to a low logic level is more than the delay time in conventional flip-flop circuit
900
.
In this way, if the clock signal is provided directly to n-channel transfer gate
74
as in flip-flop circuit
1000
, the delay time improvements deteriorate as the clock signal waveform is rounded. Thus, a speed improvement may only be realized if the clock signal waveform is near ideal. However, a clock signal may be heavily loaded and an ideal waveform may not be feasible.
In view of the above discussion, it would be desirable to provide a flip-flop circuit that may reduce a delay from an edge of a clock signal to an output of a data signal. It would also be desirable to provide a flip-flop circuit where the delay may be reduced even if a clock signal waveform is rounded. In this way, high-speed operations may be improved.
SUMMARY OF THE INVENTION
According to the present embodiments, a flip-flop circuit that may have a reduced delay time between an edge of a clock input signal and a data output signal is disclosed. A data signal may be received at a data input terminal, a clock input signal may be received at a clock signal input terminal, and data may be provided at a data output terminal. Data may be transferred from a master latch to a slave latch through a transfer circuit in response to an edge of a clock input signal. A transfer circuit may include a transfer device which may have a control terminal connected to a clock signal input terminal and a transfer device which may have a control terminal connected to a buf
Lam Tuan T.
NEC Electronics Corporation
Sako Bradley T.
Walker Darryl G.
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