Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-03-20
2003-02-04
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S211000, C327S218000
Reexamination Certificate
active
06515528
ABSTRACT:
The present invention relates to a flip-flop circuit, and particularly to a D flip-flop circuit, as detailed in the preamble to claim
1
.
Flip-flops, or bistable latches, are circuits that perform a storage function where the output signal depends both on the instantaneous value of the input signal and on the previous history. For this reason flip-flops are also referred to as sequential switching devices.
A D flip-flop is so constructed that it receives a binary input signal which is transferred to its output as a function of a clock signal CP applied to it.
FIG. 6
shows the truth table for a D flip-flop, with the output signal value Q
n+1
shown as a function of the instantaneous value of the clock signal CP
n
and the instantaneous value of the input signal D
n
. It can be seen from
FIG. 6
that the output value Q from the D flip-flop only changes when the value of the clock signal is binary ‘1’. When this is the case, the instantaneous value of the input signal D is transferred to become the output value D. In all other cases the output value Q from the D flip-flop remains unchanged. The D flip-flop can be designed to switch at either a rising or decaying edge of the clock signal.
Transistors are obvious candidates as switches for producing flip-flop circuits or bistable latch circuits. It is known that a flip-flop circuit can in particular be constructed from two directly coupled CMOS-type inverters.
There are however many applications, such as counters or shift registers, for which the simple flip-flop circuits described above are not suitable, because what are needed in this case are flip-flops which first buffer-store the state of the input signal and then only transfer it to the output when the input of the flip-flop is “blocked” again by the clock signal.
Flip-flop circuits of this kind therefore comprise two flip-flops or memory cells (latch circuits) connected in series, namely a so-called master latch and a so-called slave latch, and they are therefore also referred to as master-slave flip-flops. The master latch receives the input signal D at its input and its output is connected to the input of the slave latch. The output signal Q from the master-slave flip-flop can be picked off from the output of the slave latch. The master latch and slave latch are switched complementarily to one another by means of the clock signal CP.
If the clock signal CP=‘0’ for example, the instantaneous value of input signal D is read into the master latch and stored in it. Initially the output state Q of the slave latch remains unaltered, because the slave latch is blocked by the clock signal. When the clock signal then changes to CP=‘1’, the master latch is blocked and the instantaneous value at the output of the master latch, which had previously been read in, is transmitted to the output of the slave latch and is emitted as the output signal value Q from the master-slave flip-flop. Hence in master-slave flip-flops of this kind, in contrast to what happens in simple flip-flop circuits, there is no state of the clock signal in which the input signal D acts directly on the output signal Q.
In the citation “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings”, Jiren Yuan and Christer Svenson, IEEE Journal of Solid-State Circuits, Vol.32, No.1, January 1997, pp.62-69, a flip-flop circuit as detailed in the preamble to claim 1 is disclosed. In this citation it is proposed that a low-power D flip-flop be constructed from two differentially acting D flip-flops or memory cells (latches) connected in series. Each flip-flop comprises two directly coupled CMOS-type inverters connected in series. What in particular is proposed is that the master latch be constructed in the form of a differentially acting p-latch and the slave latch in the form of an n-latch, also differentially acting. The output signals Q,{overscore (Q)} are picked off directly from internal nodes in the slave latch. Alternatively, the output of the slave latch can be connected to a final differential memory cell or latch circuit. In this case too, the output signals Q,{overscore (Q)} are then picked off from internal nodes of the differential latch which terminates the flip-flop circuit.
Picking off the output signals Q,{overscore (Q)} from the internal node of the slave latch is however a disadvantage in that the load to be driven by the output of the flip-flop affects the slave latch and in particular it causes the slave latch to switch more slowly and a short-circuit current to flow for a long period across at least one of its two inverters.
The object of the present invention is therefore to provide a flip-flop circuit having a low power demand in which it is also possible to achieve a constant, high switching speed for the slave latch.
This object is achieved in accordance with the invention by a flip-flop circuit having the features detailed in claim 1. The subclaims define advantageous and preferred embodiments of the present invention.
In accordance with the invention the output of the flip-flop circuit is isolated from the internal nodes of the slave latch by inserting a non-differential output driver circuit. The output driver circuit may for example be designed to take the form of an inverter circuit. The isolation of the load to be driven by the output from the internal nodes of the slave latch means that it is possible to obtain for the slave latch a switching speed which is independent of the output load to be driven and which is thus high and constant. The capacitances which have to be discharged and recharged by the internal nodes of the slave latch are thus known and allow the sizes of the field-effect transistors to be optimised, in a way suited to all output loads, to give a power consumption which is as low as possible and a switching speed which is as high as possible.
In particular, the flip-flop circuit according to the invention manages with only a minimal number of clock-signal transistors, namely two clock-signal transistors. Since the clock signal is the signal in a flip-flop circuit which is subject to the most changes of state, it generally has a particularly significant bearing on the energy consumption of the flip-flop circuit.
Even without that, the flip-flop circuit according to the invention still has fewer transistors than other low-power flip-flop circuits known hitherto and can therefore be produced in a more compact form on chips. This applies particularly to the design of the master latch. The clock-signal transistor of the slave latch, which triggers the acceptance of the signal value present at the output of the master latch, is situated close to the output of the circuit, which means that there is less delay to the signal, whereas in certain solutions known previously the clock signal was processed in a number of successive stages.
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IBM Technical Disclosure Bulletin,Combined Sense Amplifier and LSSD Latch, vol. 34, No. 10A, Mar. 1992.
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R. Sharma et al.,IEEE Journal of Solid-State Circuits, 24(4);922-927 (1989).
J. YuanIEEE Journal of Solid State Circuits, 32(1):62-69 (1997).
C. Svensson et al., “Latches and Flip-Flops for Low Power Systems”, pp. 233-238.
Corless Peter F.
Edwards & Angell LLP
Infineon - Technologies AG
O'Day Christine C.
Tran Toan
LandOfFree
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