Flip-flop arrangement for a divide-by-2 frequency divider compri

Details Flip-flop arrangement for a divide-by-2 frequency divider compri Flip-flop arrangement for a divide-by-2 frequency divider compri

1989-02-21

1990-02-20

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072721, 3072722, 307279, 377119, 377121, 377127, H03K 3037, H03K 2352, H03K 3284

Patent

active

049029096

ABSTRACT:
A flip-flop (40) for a divide-by-2 frequency divider having a first stage (50) formed by two master-slave-type memory elements (10a, 10b) each having a two-input NOR gate (20a, 20b), and by a second stage (60) with 2 NOR gates (61, 62) connected as an RS flip-flop. The memory elements (10a, 10b) also include an enhancement-type MESFET transistor (30a, 30b), the gates (Ga, Gb) and the drains (Da, Db) of said transistors (30a, 30b) being coupled to the respective inputs of the NOR-gates (20a, 20b).

REFERENCES:
patent: 4300060 (1981-09-01), Yu
patent: 4544851 (1985-10-01), Conrad et al.
patent: 4801821 (1989-01-01), Prevost et al.

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