Flip-flop

Details Flip-flop Flip-flop

1998-12-08

2001-05-15

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S218000

Reexamination Certificate

active

06232810

ABSTRACT:

FIELD OF THE INVENTION
This present invention relates generally to digital circuits, and more particularly to high-speed data latching circuits, such as flip-flops, for temporarily storing digital information.
BACKGROUND OF THE INVENTION
Flip-flops are used in many applications and, in particular, in digital systems, such as processors, digital signal processors and memories.
FIG. 1
shows a circuit diagram of a prior art D flip-flop
10
. The D flip-flop
10
has a data sensing block
12
coupled to an SR latch
14
. The data sensing block
12
is well-known. A substantially similar data sensing block is described in U.S. Pat. No. 4,910,713 to Madden et al.
Typically, the SR latch
14
has a pair of cross-coupled NAND gates
16
,
18
. One input of one NAND gate
16
has a set input {overscore (S)} that receives a set signal, and one input of the other NAND gate
18
has a reset input {overscore (R)} that receives a reset signal. The SR latch
14
outputs two signals, Q and {overscore (Q)}. A high voltage level, a logical one, on the set input {overscore (S)} and a low voltage level, a logical zero, on the reset input {overscore (R)} will reset (clear) the flip-flop
14
such that the Q output has a low voltage level and the {overscore (Q)} output has a high voltage level. A high voltage level on the reset input {overscore (R)} and a low voltage level on the set input {overscore (S)} will set the SR latch
14
to a state in which the Q output has a high voltage level and the {overscore (Q)} output has a low voltage level. The SR latch
14
operates on the assumption that a low voltage level will not appear simultaneously at both the set {overscore (S)} and reset {overscore (R)} inputs. If both the set {overscore (S)} and reset {overscore (R)} inputs have a high voltage level, the SR latch
14
will not change state, but remain in its present state. A high voltage level on the set {overscore (S)} and reset {overscore (R)} inputs is considered nonactivating. The SR latch
14
can also be formed with cross-coupled NOR gates.
Referring also to
FIG. 2
, a timing diagram of the data sensing block
12
and SR latch
14
of
FIG. 1
is shown. When the clock (clk) signal is at a low voltage, the set {overscore (S)} and reset {overscore (R)} outputs of the data sensing block
12
are at a high voltage level. When the clock signal (clk) transitions high, the D input is at a low voltage and the {overscore (D)} inputis at a high voltage; therefore the set {overscore (S)} signal remains at a high voltage level while the reset {overscore (R)} signal transitions to a low voltage level as shown by arrow
21
. In response to the low voltage level of the reset {overscore (R)} signal at the NAND gate
18
input, the {overscore (Q)} signal transitions to a high voltage level, as shown by arrow
22
. In response to the high voltage level of the {overscore (S)} and {overscore (Q)} signals at the NAND gate
16
inputs, the {overscore (Q)} signal transitions to a low voltage level (arrow
23
).
Note that the delay of the NAND gate
18
determines the amount of time for the {overscore (Q)} signal to transition from a low voltage level to a high voltage level (arrow
24
) and the delay of the NAND gate
16
determines the amount of time for the Q signal to transition from the high voltage level to a low voltage level (arrow
25
).
When the D inputis at a high voltage level and the {overscore (D)} inputis at a low voltage level and the clock signal (clk) transitions high, the NAND gates
16
and
18
also determine the amount of time for the Q and {overscore (Q)} signals to transition to a high voltage level and a low voltage level, respectively.
The inventors identified that the cross-coupled NAND gates
16
,
18
of the SR latch
14
limit the speed of the D flip-flop
10
. The cross-coupled NAND gates
16
,
18
are a single stage which simultaneously generates and latches the Q and {overscore (Q)} signals. When either the set or reset signal transitions from a high to a low voltage level, the set {overscore (S)} and reset {overscore (R)} signals must pass through two NAND gates
16
,
18
to generate the Q and {overscore (Q)} outputs. Therefore the SR latch
14
has two gate delays between a change of the voltage level on the set {overscore (S)} or reset {overscore (R)} inputs and the rising and falling edges at the Q and {overscore (Q)} outputs. This degrades the speed of the circuit by more than 70%. Moreover, at the process limits, the speed further degrades and the amount of speed degradation can exceed 100%.
In
FIG. 3
, a similar circuit
20
to the circuit shown in
FIG. 1
is used in another prior art D flip-flop. The circuit
20
of
FIG. 3
is similar to the circuit
10
of
FIG. 1
except that the transistor N
6
(
FIG. 1
) is not used. Transistor N
6
ensures the static operation of the data sensing block
12
of the flip-flop
10
for low-power applications. Transistor N
6
does not have significant impact on the speed of the flip-flop
10
. Since the SR latch
14
of
FIG. 3
is the same as the SR latch
14
of
FIG. 1
, the D flip-flop
20
of
FIG. 2
has similar performance problems to the D flip-flop of FIG.
1
.
Processor speed and performance is ever-increasing. Therefore a flip-flop that operates at a higher speed is desirable.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved flip-flop that operates at a higher processor speed.
It is another objective of the present invention to provide an SR latch that operates at a higher speed.
These and other objectives and advantages of the present invention are generally achieved by an SR latch that separates the generation of the Q and {overscore (Q)} signals from the latching or storage function. A generation block generates the appropriate Q and {overscore (Q)} signals based on the set and reset input signals, then a storage block latches the Q and {overscore (Q)} signals, thereby eliminating the two gate delays of the cross-coupled NAND gates of the prior art.
More particularly, the generation block has first and second logic blocks for generating the Q and {overscore (Q)} signals, respectively, from set and reset signals. The first and second logic blocks also have an inactive state. A static storage block receives the Q and {overscore (Q)} signals and maintains the Q signal and {overscore (Q)} signals at the voltage level that was output prior to when the first and second logic blocks become inactive.
In another embodiment, a D flip-flop has a sensing block coupled to the SR latch of the present invention.
A method of operating an SR latch is also provided in which set and reset signals are received. Q and {overscore (Q)} signals are generated from the set and reset signals. The Q and {overscore (Q)} signals have complementary states. After the Q and {overscore (Q)} signals are generated, the complementary states of the Q and {overscore (Q)} signals are latched.
Other features and advantages of the present invention will become apparent to a person skilled in the art who studies the present invention disclosure. Therefore, a more detailed description of a preferred embodiment of the invention is given with respect to the following drawings.


REFERENCES:
patent: 4845675 (1989-07-01), Krenik et al.
patent: 4910713 (1990-03-01), Maden et al.
patent: 5124568 (1992-06-01), Chen et al.
patent: 5192878 (1993-03-01), Miyamoto et al.
patent: 5793236 (1998-08-01), Kosco
S.H. Unger, et al., “Clocking Schemes for High-Speed Digital Systems,” (Oct. 1986) IEEE Transactions on Computers, vol. C-35, No. 10, pp. 880-895.
J. Montanaro, et al., “A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor,” (Nov. 1996) IEEE Journal of Solid-State Circuits, vol. 31, No. 11, pp. 1703-1712.
B.A. Gieseke, et al., “FA 10.7: A 600MHz Superscaler RISC Microprocessor with Out-Of-Order Execution,” IEEE International Solid-State Circuits Conference, pp. 176-177.
G.J. Fisher, “An Enhanced Power Meter for SPICE2 Circuit Simulation,” (May 1988) IEEE Transactions on Computer-Aided Design, vol. 7, No. 5, pp. 641-643.
D.W. Dobberpuhl, “C

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