Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
1999-08-04
2001-07-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S107000, C438S118000
Reexamination Certificate
active
06255143
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit (IC) devices, and more particularly, to a method to enhance the heat flow between flip-chip BGA devices and the motherboard. The method of the invention also reduces the length of the signal paths between the Integrated Circuit device and the package terminal.
(2) Description of the Prior Art
High density interconnect technology frequently leads to the fabrication of multilayer structures in order to connect closely spaced integrated circuits with each other. A single substrate serves as an interconnect medium to which multiple chips are connected thereby forming a device package with high packaging density and dense chip wiring. The metal layers that make up the interconnect network and the via and contact points that establish connections between the interconnect networks are separated by layers of dielectric (such as polyimide) or insulating layers. In the design of the metal interconnects, strict rules must be adhered to in order to avoid problems of package performance and reliability. For instance, the propagation directions of primary signals must typically intersect under 90 degree angles to avoid electrical interference between adjacent lines. It is further required that planarity is maintained throughout the construction of multilayer chip packages for considerations of photolithography and package reliability. Many of the patterned layers within such a structure form the base for subsequent layers and their lack of planarity can therefore have a multiplying effect on overlying layers.
Quad Flat Packages (QFP) have in the past been used to created surface mounted, high pin count integrated packages with various pin configurations. The electrical connections with these packages are typically established by closely spaced leads that are distributed along the four edges of the flat package. This limits the usefulness of the QFP since a high I/O count cannot be accommodated in this manner. To address this problem, the Ball Grid Array (BGA) package has been created whereby the I/O points for the package are distributed not only around the periphery of the package but over the complete bottom of the package. The BGA package can therefore support more I/O points making this a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mils spacings in a regular or staggered pattern.
Where circuit density keeps increasing and device features continue to be reduced in size, the effect of the interconnect metal within the package becomes relatively more important to the package performance. Factors that have a negative impact on circuit performance, such as line resistance, parasitic capacitance, RC delay constants, crosstalk and contact resistance have a significant impact on the package design and its limitations. A significant power drop may for instance be introduced along the power and ground buses where the reduction of the interconnect metal does not match the reduction in device features. Low resistance metals (such as copper) are therefore finding wider application in the design of dense semiconductor packages.
Increased I/O combined with increased high demands for high performance IC's has led to the development of Flip Chip packages. Flip chip technology fabricates bumps (typically Pb/Sn solder) on Al pads and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to mote sophisticated substrates that accommodate several chips to form larger functional units.
The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and Coefficient of Thermal Expansion (CTE) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the CTE mismatch can cause a large thermal stress on the solder lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
Prior Art substrate packaging uses ceramic and plastic BGA packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall package. Recent years have seen the emergence of plastic BGA packaging, this packaging has become the main stream design and is frequently used in high volume BGA package fabrication. The plastic substrate BGA package performs satisfactorily when used for low-density flip-chip IC's. If the number of pins emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the IC is less than 350 but the required overall package size is small, or if the chip power dissipation is high (in excess of 4 Watts per chip), the plastic structure becomes complicated and expensive.
In mounting a large number of flip chip packages, the following aspects are key aspects in the design of the interfaces onto which the flip chip dies are mounted:
interconnect of the flip-chip contact points to the surrounding electrical components
thermal transmission between the flip-chip and its environment and
firmness of the overall package that contains the large number of flip-chips.
Interconnecting of the flip-chip contact points to the surrounding electrical components can be accomplished by mounting the flip chip on the surface of a package substrate or by interconnecting the flip-chip to a circuit type that contains the interconnect lines. The contact points of the flip-chip IC device make contact with contact points in the circuit, the circuit re-distributes (fan-out) the flip-chip IC device to the contact points. The interconnect lines contained within the circuit are connected to contact balls that are mounted on the device or on the motherboard and form the interface between the final package assembly and the motherboard. It must thereby also be understood that the original contact balls of the flip chip IC device are encased in a material (for instance epoxy) for protection of these balls. The epoxy is therefore encased between the lower surface of the flip-chip IC device and the upper surface of the flex circuit. This epoxy is referred to as underfill since it is filled in under the original flip-chip device.
Firmness of the overall package is assured by mounting the flip-chip devices on the surface of a motherboard, the motherboard provides, in addition to electrical interconnects, the rigidity of the overall package.
Thermal transmission between the flip-chip and its environment is assured by providing a heat sink that is typically attached to the flex circuit.
The invention addresses the aspect of thermal transmission between the flip-chip and its environment. The invention teaches a method that provides excellent heat flow properties whereby the heat that is generated in the die is removed from both the top and the bottom surface of the die. The invention further provides for a reduction in the length of the signal path since signals travel directly from the IC device to the circuit contact balls without having to travel through vias or other transmission paths.
U.S. Pat. No. 5,898,224 (Akram) shows a Flip chip assembly with underlayer and a heat sink and an outer top encapsulant.
U.S. Pat. No. 5,883,430 (Johnson) shows a flip chip encapulated on the bottom and sides, a heat sink on top and an underlayer.
U.S. Pat. No. 5,817,545 (Wang et al.) teaches a process for underfill for a flip chip.
Ackerman Stephen B.
Lattin Christopher
Niebling John F.
Saile George O.
St. Assembly Test Services Pte Ltd.
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