Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-07-23
2004-12-14
Graybill, David E. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S777000, C257S782000
Reexamination Certificate
active
06831361
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a method for connecting one substrate, such as a flip-chip type semiconductor die, to another substrate, such as a silicon wafer, printed circuit board, or other substrate (hereinafter referred to generally as a “substrate”). More particularly, the present invention relates to a semiconductor die having a raised bond pad attached to a substrate which also has raised bond pads aligned to make electrical contact with the die bond pad without attachment.
2. State of the Art
A flip chip is a semiconductor chip or die that has bumped terminations spaced around the active surface of the die and is intended for face-to-face attachment to a substrate or another semiconductor die. The bumped terminations of the flip chips are usually a “Ball Grid Array” (“BGA”) configuration wherein an array of minute solder balls is disposed on an attachment surface of a semiconductor die, or a “Slightly Larger than Integrated Circuit Carrier” (“SLICC”) configuration wherein an array of minute solder balls is disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA.
The attachment of a flip chip to a substrate or another semiconductor involves aligning the solder balls on the flip chip with a plurality of contact points (configured to be a mirror image of the solder ball arrangement on the flip chip) on a facing surface of the substrate. A plurality of solder balls may also be formed on a facing surface of the substrate at the contact points. A quantity of liquid flux is often applied to the face of the chip and/or substrate, and the chip and substrate are subjected to elevated temperature to effect refluxing or soldering of the solder balls on the chip and/or corresponding solder balls on the substrate.
There are numerous variations to the standard flip chip attachment technique. For example, U.S. Pat. No. 5,329,423 issued Jul. 12, 1994 to Scholz relates to a demountable flip-chip assembly comprising a first substrate having a contact site with a raised bump and a second substrate having a depression for a contact site. The raised bumps are pressed into the depressed areas to electrically and mechanically connect the first substrate to the second substrate without using reflowed solder. Thus, the first substrate can be removed from the second substrate without damaging either substrate.
U.S. Pat. No. 5,477,086 issued Dec. 19, 1995 to Rostoker et al. relates to a flip chip attachment technique involving forming a concave conductive bump on one substrate (such as the PCB) to receive and align the solder balls on the other substrate (such as the semiconductor die). The solder balls and/or the concave conductive bump are reflowed to fuse them together.
It is also known in the art that conductive polymers or resins can be utilized in place of solder balls. U.S. Pat. No. 5,258,577 issued Nov. 2, 1993 to Clements relates to a substrate and a semiconductor die with a discontinuous passivation layer. The discontinuities result in vias aligned with the contact points between the substrate and the semiconductor die. A resin with spaced conductive metal particles suspended therein is disposed within the vias to achieve electrical contact between the substrate and the semiconductor die. U.S. Pat. No. 5,468,681 issued Nov. 21, 1995 to Pasch relates to interconnecting conductive substrates using an interposer having conductive plastic filled vias.
Such flip chip and substrate attachments (collectively “electronic packages”) are generally comprised of dissimilar materials that expand at different rates on heating. The most severe stress is due to the inherently large thermal coefficient of expansion (“TCE”) mismatch between the plastic and the metal. These electronic packages are subject to two types of heat exposures: process cycles, which are often high in temperature but few in number; and operation cycles, which are numerous but less extreme. If either the flip chip(s) and/or substrate(s) are unable to repeatedly bear their share of the system thermal mismatch over its lifetime, the electronic package will fracture, thereby destroying the functionality of the electronic package.
As an electronic package dissipates heat to its surroundings during operation, or as the ambient system temperature changes, differential thermal expansions cause stresses to be generated in the interconnection structure (solder ball bonds) between the semiconductor die and the substrate. These stresses produce instantaneous elastic and, most often, plastic strain, as well as time-dependent (plastic and elastic) strains in the interconnection structure, particularly at the weakest interconnection structure. Thus, the thermal expansion mismatch between chip and substrate will cause a shear displacement to be applied on each terminal which can fracture the solder connection.
The problems associated with thermal expansion match are also applicable to connections made with conductive polymers or resins. After curing, the polymers or resins become substantially rigid. The rigid connections are equally susceptible to breakage due to thermal expansion mismatch.
Therefore, it would be advantageous to develop an apparatus for connecting a first semiconductor die or substrate to a second semiconductor die or substrate in such a manner that electrical contact is made at the contact points but no mechanical attachment occurs at the contact point. Such a connection would eliminate the possibility of fractures occurring at the contact points.
SUMMARY OF THE INVENTION
The present invention relates to an apparatus and a technique for connecting a first substrate to a second substrate wherein the first substrate has a plurality of raised bond pads which make electrical contact (without attachment) with a plurality of raised bond pads on the second substrate.
preferred method for constructing the apparatus of the present invention comprises providing a first substrate having a plurality of leads on an active surface or within the first substrate. A plurality of conductive bumps which contacts the leads is formed on the active surface of the first substrate. The conductive bumps are preferably metallic, such as copper, aluminum, or the like, and are formed by any number of known industry techniques, such as photolithography (subtractive or additive etching), liquid photoresist, dry-film photoresist, silk screening, or the like. The conductive bumps are also preferably flat on an upper surface of the conductive bumps.
A silicon wafer is preferred as the first substrate because the silicon wafer is usually very smooth and planar due to the chemical mechanical polishing (planarizing) or “CMP” step in silicon wafer production. A smooth and planar surface is preferred so that the conductive bumps are of even height across the silicon wafer.
A second substrate is provided which preferably also has a plurality of leads on an active surface or within the second substrate. A plurality of conductive bumps which contacts the leads is formed on the active surface of the second substrate in the same manner as described for the first substrate. The conductive bumps are preferably the same metallic material as the first substrate conductive bumps or at least a very similar metallic material. The conductive bumps are also preferably flat on a facing surface of the conductive bumps.
The second substrate is preferably a flip chip, such as a memory chip, a CPU, or a logic chip. Flip chips are generally manufactured with a plurality of bond pads on an active surface wherein each bond pad is connected to a lead. A facing surface of each bond pad has the conductive bump formed thereon.
A passivation layer is applied over the second substrate active surface. The passivation layer is preferably thicker than the height of the second substrate conductive bumps. The passivation layer is etched by any known industry standard technique to form vias to expose an active surface of the second substrate co
Graybill David E.
Micro)n Technology, Inc.
TraskBritt
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