Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-09-06
2004-08-03
Chambliss, Alonzo (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S613000, C228S180220
Reexamination Certificate
active
06770510
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to aspects of providing an underfill and of applying solder flux in creating flip-chip semiconductor device packages.
(2) Description of the Prior Art
Flip chip technology is a technique whereby interconnections are made between a first array of contact points provided over an active surface of a semiconductor chip and a second array of contact points provided over the surface of a flip chip supporting substrate. Typically, solder bumps are provided as terminals over the active surface of the flip chip, these solder bumps are aligned and bonded with contact pads provided over the surface of a substrate that serves as a semiconductor device mounting support.
Flip chip bonding provides advantages of a reduction in the interconnection length, a smaller package footprint and allows for a lower package profile when compared with conventional wire bond packages. Most significantly however is the advantage that is offered by the flip chip technology of significantly extending input/output capabilities of the mounted chip since the flip chip technology is not limited to providing points of I/O interconnect of the mounted chip in accordance with a particular pattern or array but can provide points of I/O interconnect across the entire active surface of the mounted device. The limitation that is in this case still in place is a limitation of the pitch or spacing by which the points of electrical contact can be created over the interfacing surfaces.
One of the methods that has been employed for mounting semiconductor devices over a supporting substrate comprises the use of Ball Grid Array (BGA) contact points, whereby a pattern of closely spaced contact balls or solder bumps over the active surface of the chip is used to provide interconnection between the flip chip and a supporting, frequently ceramic based, substrate. This approach, although allowing for extended I/O capabilities, presents problems of contact ball and solder joint reliability. This latter problem is greatly exacerbated by impact of thermal cycling during the creation of the semiconductor device package and by excessive mechanical stress that is exerted on one or more of the applied contact balls due to lack of planarity of the interfacing points of contact.
The art has long used the method of providing underfill to offset negative effects of lifetime fatigue that is typically experienced by solder connections in a flip chip interconnect arrangement. This approach applies an epoxy-based underfill in the voids between the active surface of the flip chip and the surface of the supporting substrate over which the flip chip is mounted. The underfill completely surrounds the aligned and joined points of interfacing electrical contacts, including the solder balls that are used for this purpose. This underfill is used to distribute stress over larger areas from areas where this stress is typically concentrated. For instance, points of electrical contact are ideally located in one plane, as are the points of the matching and therewith aligned points of electrical contact. Where this planarity is not adhered to, the first matched points that make contact with each other bear an unusual large burden of the contacting forces, leading to extreme stress on these first contacting points of electrical contact.
Underfill can further beneficially be used to offset effects of thermal stress by for instance matching the Thermal Coefficient of Expansion (CTE) of the underfill with the CTE of the interfacing solder connections. Additional advantages that can be derived from the application of underfill are issues of chip protection from environmental influences such as moisture and from mechanical damage caused by for instance shock and vibration of the completed chip package.
The invention provides a method of mounting a flip chip over a supporting substrate whereby no underfill is applied, thereby eliminating a number of disadvantages, which will be highlighted at a later time, that are typically incurred by the application of flip chip underfill. The invention further provides for the creation of a flip chip packages whereby the need for solder flux application is removed.
U.S. Pat. No. 6,284,086 (Cardellino et al.) shows an underfill process for flip chips.
U.S. Pat. No. 6,168,972 (Wang et al.) reveals a flip chip pre-assembly underfill process.
U.S. Pat. No. 6,051,489 (Young et al.) discloses a flip chip pre-assembly underfill process.
U.S. Pat. No. 6,268,114 B1 (Wen et al.) shows a underfill of a solder window in a flip chip process.
SUMMARY OF THE INVENTION
A principle objective of the invention is to create a flip chip device package that can be assembled without the application of solder flux.
Another objective of the invention is to create a flip chip device package whereby the conventional method of providing an underfill for the package is replaced by a more effective method.
In accordance with the objectives of the invention a new method is provided to remove the conventional accumulation of a layer of tin oxide over the surface of solder bumps by means of fluorine based plasma treatment of the solder bumps. In addition, an improved method is provided for the application of underfill that replaces the conventional method of providing an underfill for a packaged flip chip device.
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Ackerman Stephen B.
Chambliss Alonzo
Saile George O.
Taiwan Semiconductor Manufacturing Company
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