Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-10-10
2002-12-03
Faburyl, Wael (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S001000, C438S612000, C438S974000
Reexamination Certificate
active
06489180
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to flip-chip packaging technology, and more particularly, to a flip-chip packaging process, which utilizes a no-flow underfill technique to help prevent neighboring solder bumps from being short-circuited to each other during solder-reflow, and which is characterized in the provision of sharp-pointed studs over substrate-side bond pads to help assure reliable electrical bonding between chip-side solder bumps and substrate-side bond pads without being made open-circuited by the electrically-insulative material being used for flip chip underfill.
2. Description of Related Art
The flip-chip technology is an advanced semiconductor fabrication technology that allows the overall package size to be made very compact. The flip-chip package configuration differs from conventional ones particularly in that it mounts the semiconductor chip in an upside-down manner over the chip carrier and electrically coupled to the same by means of solder bumps provided on the active surface of the semiconductor chip. Since no bonding wires are required, which would otherwise occupy much layout space, the overall size of the flip-chip package can be made very compact as compared to conventional types of semiconductor device packages.
After the flip chip is readily bonded in position, however, a gap would be undesirably left between the flip chip and the substrate. Since the chip and the substrate are typically different in coefficient of thermal expansion (CTE), if the gap is not underfilled, it would easily cause the flip chip to suffer from fatigue cracking and electrical failure due to thermal stress while undergoing high-temperature conditions during subsequent processes. As a solution to this problem, it is an essential step in flip-chip package fabrication to perform a flip-chip underfill process so as to fill an electrically-insulative material, such as epoxy resin, into the flip chip gap. The underfilled resin, when hardened, can serve as a mechanical reinforcement to the flip-chip construction to cope against thermal stress.
Conventionally, the flip-chip packaging process is performed in the following successive steps: (1) chip mounting; (2) solder reflow; and (3) dispensing underfill material. In this case, the underfill material is dispensed onto the substrate after the flip chip is readily mounted in position and the solder-reflow process is completed. The dispensed underfill material will then flow through capillary action into the gap under the flip chip.
However, by today's semiconductor fabrication technology, the pitch between neighboring solder bumps can be made very small; and consequently, the solder bumps during the solder-reflow step would easily come in touch with neighboring ones, making them short-circuited to each other. If any solder bumps are short-circuited, the finished flip-chip device would be regarded as defective. One solution to this problem is to use the so-called no-flow underfill technique, by which the underfill material is dispensed onto the substrate before the flip chip is mounted on the substrate. In this case, the flip-chip packaging process is performed in the following successive steps: (1) dispensing underfill material; (2) chip mounting; and (3) solder reflow. Since the pre-dispensed underfill material can provide an insulative effect to the solder bumps during the solder-reflow process, it can help prevent the solder bumps from being short-circuited to each other.
FIGS. 1A-1D
are schematic sectional diagrams used to depict a conventional flip-chip packaging process which utilizes no-flow underfill technique to help prevent neighboring solder bumps from being short-circuited to each other during the solder-reflow process.
Referring to
FIG. 1A
, in the flip-chip packaging process, the first step is to prepare a semiconductor chip
110
and a substrate
120
for flip-chip application. The semiconductor chip
110
is formed with a plurality of solder bumps
111
over the active surface thereof, while the substrate
120
is formed with a plurality of corresponding bond pads
121
on the top surface thereof (note that
FIG. 1A
is simplified to show only the parts related to the invention; the actual semiconductor chip and substrate may include a great number of various other components).
The substrate-side bond pads
121
can be either SMD (Solder Mask Define) type, or NSMD (Non-SMD) type, or mixed SMD-NSMD type. These types of bond pads are all well-known in the semiconductor industry, so description thereof will not be further detailed.
Referring further to
FIG. 1B
, in the next step, an underfill material, such as epoxy resin, is dispensed over the top surface of the substrate
120
so as to form a no-flow underfill layer
130
over the top surface of the substrate
120
, which covers all the substrate-side bond pads
121
.
Referring further to
FIG. 1C
, in the next step, the semiconductor chip
110
is mounted in an upside-down (flip chip) manner onto the substrate
120
, with the solder bumps
111
thereof being aligned respectively to the substrate-side bond pads
121
. The semiconductor chip
110
is then forcibly pressed down so as to allow the solder bumps
111
to come into firm abutment on the substrate-side bond pads
121
.
Undesirably, however, due to the existence of the previously formed no-flow underfill layer
130
, the solder bumps
111
may not be reliably abutted on the substrate-side bond pads
121
. In the case of
FIG. 1C
, for example, assume one of the solder bumps
111
is unabutted on the corresponding one of the substrate-side bond-pads
121
, as the one indicated by the dotted circle
140
.
Referring further to
FIG. 1D
, in the next step, a solder-reflow process is performed to reflow all the solder bumps
111
over the substrate-side bond pads
121
. During this process, however, since the solder bump indicated by the dotted circuit
140
has been unabutted on its associated one of the substrate-side bond pads
121
, it would be hardly wetted to the associated one of the substrate-side bond pads
121
, thus undesirably making the electrical bonding therebetween failed to be reliably established.
Various patented technologies have been proposed for flip-chip applications. A few of these patented technologies are listed in the following:
U.S. Pat. No. 5,736,790 entitled “SEMICONDUCTOR CHIP, PACKAGE AND SEMICONDUCTOR DEVICE”;
U.S. Pat. No. 5,858,149 entitled “PROCESS FOR BONDING SEMICONDUCTOR CHIP”;
U.S. Pat. No. 5,904,859 entitled “FLIP CHIP METALLIZATION”;
U.S. Pat. No. 5,902,686 entitled “METHODS FOR FORMING AN INTERMETALLIC REGION BETWEEN A SOLDER BUMP AND AN UNDER BUMP METALLURGY LAYER AND RELATED STRUCTURES”;
U.S. Pat. No. 6,015,652 entitled “MANUFACTURE OF FLIP-CHIP DEVICE”;
U.S. Pat. No. 5,137,845 entitled “METHOD OF FORMING METAL CONTACT PADS AND TERMINALS ON SEMICONDUCTOR CHIPS”;
U.S. Pat. No. 5,773,359 entitled “INTERCONNECTION SYSTEM AND METHOD OF FABRICATION”;
U.S. Pat. No. 5,736,456 entitled “METHOD OF FORMING CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONS”;
U.S. Pat. No. 4,927,505 entitled “METALLIZATION SCHEME PROVIDING ADHESION AND BARRIER PROPERTIES”;
U.S. Pat. No. 5,903,058 entitled “CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATION”.
However, none of the above-listed patented technologies can help solve the aforementioned problem of unreliable electrical bonding between chip-side solder bumps and substrate-side bond pads when no-flow underfill technique is utilized.
SUMMARY OF THE INVENTION
It is therefore an objective of the invention to provide a flip-chip packaging process, which can help assure reliable electrical bonding between chip-side solder bumps and substrate-side bond pads.
In accordance with the foregoing and other objectives, the invention proposes an improved flip-chip packaging process.
Broadly recited, the flip-chip packaging process of the invention comprises the following procedural steps: (1) preparing a semiconductor chip and a substrate for flip-chip application; the semiconductor chip being formed wi
Chiu Shih Kuang
Tsai Ying Chou
Collins D. M.
Corless Peter F.
Edwards & Angell LLP
Faburyl Wael
Jensen Steven M.
LandOfFree
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