Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2005-09-27
2005-09-27
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S108000, C438S125000
Reexamination Certificate
active
06949404
ABSTRACT:
Provided are a semiconductor flip chip package with warpage control and fabrication methods for such packages. The packages of the present invention include heat spreader lids that are rigidly attached to the die or packaging substrate with a bond that can withstand the considerable bowing pressures caused by the CTE mismatch between the die and substrate. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the PCB board to which it is ultimately bound. Package reliability is thereby also enhanced, particularly for large die sizes.
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U.S. Appl. No.: 10/719,451 filed on Nov. 20, 2003 entitled:Structure And Material For Assembling A Low-K Sl Die To Achieve A low Warpage And Industrial Grade Reliability Flip Chip Package With Organic Substrate.
U.S. Appl. No.: 10/849,651 filed May 19, 2004 entitled:Low Stress And Warpage Laminate Flip Chip BGA Package.
Fritz Don
Li Yuan
Wang Wen-chou Vincent
Altera Corporation
Beyer Weaver & Thomas LLP
Nguyen Ha Tran
Roman Angel
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