Flip chip package substrate

Details Flip chip package substrate Flip chip package substrate

2003-04-03

2004-03-30

Vigushin, John B. (Department: 2827)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C174S260000, C174S262000, C257S723000

Reexamination Certificate

active

06714421

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91117856, filed Aug. 08, 2002.
BACKGROUND OF THE INVENTION
The present invention relates to a chip package substrate, and in particular to a flip chip package substrate which can be flip chip interconnected to a set of chips having pads in a same similar pad arrangement but with different pad pitches.
Flip Chip Interconnect Technology (FC) essentially makes use of area array method to deposit pads onto the active surface of the chip, and bumps are formed respectively onto the pads. After the chip is flipped over, the bumps on the chip are used to correspondingly connect to contacts of the carrier. Thus, the chip can be electrically connected to the carrier via the bumps, and via the inner circuit of the carrier, the chip can be electrically connected to the external electronic device. Due to the fact that flip chip technology is suitable for a chip package with a high pin count and has the advantages of minimizing chip package area and minimizing short message transmission path, such that flip chip interconnect technology has been widely applied in the field of chip package. Currently, commonly found chip package structure has employed the flip chip interconnect technology includes a few types of chip package structure, such as Flip Chip Ball Grip Array (FCBGA) and Flip Chip Pin Grid Array (FCPGA).
Referring to
FIG. 1
, which shows a sectional view of a conventional flip chip ball grid array (FCBGA) type of a chip package structure. The active surface
12
of the flip chip
10
is provided with a plurality of pads
14
for signal transmission output terminals of the chip
10
. The pads
14
are provided individually with a bump
30
for connection to the bump pads
24
deposited on the top face of the flip chip package substrate
20
. The substrate
20
is formed from the stacking of a plurality of patterned conductive layers
23
and a plurality of insulation layers
26
. A plurality of conductive vias
28
respectively pass through the insulation layers
26
to electrically connect two or more than two layers of conductive layers
23
, wherein the conductive vias
28
include through holes
28
a
and vias
28
b
. The through holes and the vias are of different sizes as a result of different fabrication processes. Further, the bump pads on the top face
21
of the substrate
20
are formed of these top layers (conductive layer
23
a
). Solder mask
27
a
is used to protect the conductive layer
23
a
and at the same time to expose the bump pads
24
formed of the conductive layer
23
a.
Referring to
FIG. 1
, the bottom face
22
of the substrate
20
is deposited with a plurality of ball pads
25
which are formed of the lowest one of the conductive layer
23
(e.g. conductive layer
23
b
). And similarly, a patterned solder mask
27
b
is used to protect the conductive layer
23
b
and at the same time to expose the ball pads of the conductive layer
23
b
. The ball pads
25
can be respectively deposited a ball
40
or other conductive structure thereon so as to electrically connect the ball pads
25
to the external electronic device. Thus, via bumps
30
, the pads
14
of the chip
10
can be electrically and mechanically connected to the corresponding bump pads
24
of the substrate
20
. Then via the inner circuit formed of conductive layers
23
and conductive vias
28
, the pads
14
of the chip
10
can route to the ball pads
25
on the bottom face
22
of the substrate
20
. Finally, via the balls
40
on the ball pads
25
or other conductive structures, the pads
14
of the chip
10
can be electrically and mechanically connected to the electronic device of next level, for instance PCB.
Referring to
FIG. 1
, when the area of the chip
10
is reduced, the pitches of the pads
14
on the chip
10
will be reduced proportionally. As a result the positions of the bump pads
24
on the substrate
20
must respectively correspond to the positions of the pads
14
of the chip with reduced area. Accordingly, the substrate
20
has to be re-designed, in particular the positions of all the bump pads
24
of the substrate
20
must be re-designed. Thus, the process time of the flip chip package of the chip
10
cannot be effectively reduced.
SUMMARY OF THE INVENTION
In view of the above, the object of the present invention is to provide a flip chip package substrate which can connect to a set of chips having pads in a similar pad arrangement but with different pad pitches by flip chip bonding. Therefore, these chips can co-share a flip chip package substrate. Thus, the design procedure for a new flip chip package substrate can be reduced, and therefore the process time of chips connected onto the flip chip package is reduced.
According to the object of the present invention, the present invention provides a flip chip package substrate suited for flip chip bonding to either a first chip or a second chip, wherein the first chip is provided with a first active surface and a plurality of first pads, and the first pads are deposited on the first active surface, and the second chip is provided with a second active surface and a plurality of second pads, and the second pads are deposited on the second active surface corresponding to the arrangement of the first pads. The flip chip package substrate comprises: a plurality of patterned conductive layers inter-stacked in sequence; at least an insulation layer positioned between two adjacent conductive layers for isolation the conductive layers and is inter-stacked with the conductive layers; and a plurality of conductive vias respectively passing through the insulation layer for electrically connection of the conductive layers; wherein the top layer of the conductive layers is provided with a plurality of bump pad groups and the groups are respectively provided with a first bump pad and a second bump pad, and the first bump pad and the second bump pad of the same bump pad group are electrically connected with each other, and the positions of the first bump pads are respectively corresponding to the positions of the first pads of the first chip, and the positions of the second bumps are respectively corresponding to the positions of the second pads of the second chip.


REFERENCES:
patent: 4489365 (1984-12-01), Daberkoe
patent: 5237131 (1993-08-01), Catlin
patent: 6011695 (2000-01-01), Dumke

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