Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2003-08-13
2004-10-26
Ngo, Hung V. (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S738000, C257S778000, C257S781000, C174S050510
Reexamination Certificate
active
06809262
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 92210189, filed Jun. 3, 2003.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a chip carrier. More particularly, the present invention relates to a flip chip package carrier for flip chip bonding.
2. Description of the Related Art
With the rapid progress in manufacturing techniques in recent years, many high-tech, personalized and multi-functional electronic products are available in the market. All these products are designed to be light, portable and compact. In the semiconductor industry, chip carrier is a commonly used packaging element. The most common chip carrier mainly comprises a plurality of alternately laid circuit layers and dielectric layers. The dielectric layer is inserted between neighboring patterned circuit layers. By plating a through hole (PTH) or a via, the patterned circuit layers are electrically interconnected. Since the chip carrier has a dense and compact circuit layout and good electrical performance, it has become the principle substrate for forming a flip chip package.
In most flip chip package, the chip is electrically connected to a substrate in a flip chip bonding operation. In general, one of the substrate surfaces has a plurality of bonding pads thereon for bonding with various conductive bumps. The copper bonding pads are actually portions of the outermost patterned circuit layer. Furthermore, a solder mask layer covers the trace lines in the outermost patterned circuit layer. According to whether the bonding pads are covered by a solder mask layer or not, the bonding pads are said to have a ‘solder mask defined’ (SMD) or a ‘non-solder mask defined’ (NSMD) configuration.
FIG. 1A
is a localized top view of a conventional flip chip package carrier having NSMD bonding pads thereon.
FIG. 1B
is a cross-sectional view along line I—I of FIG.
1
A. As shown in
FIGS. 1A and 1B
, the flip chip package carrier has a substrate
100
with a surface
102
having a plurality of bonding pads
112
a
thereon. The bonding pads
112
a
are actually portions of the outermost patterned circuit layer
110
. Furthermore, a patterned solder mask layer
140
a
covers the surface
102
of the substrate
100
so that the trace lines
114
in the patterned circuit layer
110
is protected. In addition, the patterned solder mask layer
140
a
has a plurality of solder mask openings
142
a
that exposes the bonding pads
112
a
. Because each solder mask openings
142
a
of the solder mask layer
140
a
has an area larger than the bonding pad
112
a
and exposes the upper and the side surface of the bonding pad
112
a
, this type of bonding pads
112
a
is defined as a non-solder mask defined (NSMD) bonding pad.
FIG. 2A
is a localized top view of a conventional flip chip package carrier having SMD bonding pads thereon.
FIG. 2B
is a cross-sectional view along line II—II of FIG.
2
A. As shown in
FIGS. 2A and 2B
, the flip chip package carrier has a substrate
100
with a surface
102
having a plurality of bonding pads
112
b
thereon. The bonding pads
112
b
are actually portions of the outermost patterned circuit layer
110
. Similarly, a patterned solder mask layer
140
b
covers the surface
102
of the substrate
100
so that the trace lines
114
in the patterned circuit layer
110
is protected. The patterned solder mask layer
140
b
has a plurality of solder mask openings
142
b
that exposes the bonding pads
112
b
. However, because each solder mask openings
142
b
of the solder mask layer
140
b
has an area smaller than the bonding pad
112
b
and exposes only the upper surface of the bonding pad
112
b
, this type of bonding pads
112
a
is defined as a solder mask defined (SMD) bonding pad.
With great advances in the manufacturing technique, the size of each chip is reduced correspondingly. That means, for a high-pin-count flip chip package, distance of separation between the conductive bumps is getting smaller. In other words, the distance separating each bonding pad from its neighboring trace lines must be reduced so that a denser circuit layout and a higher bonding pad density is obtained. Yet, it does not matter if the SMD or the NSMD type of bonding pads is used. If there is to be any reduction in the distance of separation between the bonding pad and its neighboring trace line, equipment with a higher level of alignment accuracy is required to form the solder mask layer and the solder mask openings. The higher alignment accuracy prevents the shifting of the solder mask opening to result in an exposure of a neighboring trace line. If the bonding pad and its neighboring trace line are really exposed by the same solder mask opening due to an excessive misalignment, both the bonding pad and the trace line may come in contact with a conductive bump to cause a short circuit. Yet, using equipment with a high alignment precision to form the solder mask layer and the solder mask openings is likely to incur a high cost for producing the substrate.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a flip chip package carrier whose solder mask layer and solder mask openings can be fabricated using processing equipment having a lower alignment accuracy to reduce production cost.
A second object of this invention is to provide a flip chip package structure having a substrate whose distance of separation between a die pad and its neighboring trace lines is reduced so that the substrate can have a denser circuit layer and a higher bonding pad density.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a flip chip package carrier. The flip chip package carrier comprises a substrate, a patterned circuit layer, a first solder mask layer and a solder layer. The patterned circuit layer is set on the surface of the substrate. Moreover, the substrate has a plurality of bonding pads thereon. The first solder mask layer covers the surface of the substrate but has a first solder mask opening that expose various bonding pads. Furthermore, the solder layer covers the upper and side surfaces of the bonding pads.
This invention also provides a flip chip package structure comprising a substrate and a chip. The substrate has a plurality of bonding pads and a solder mask layer thereon. The solder mask layer has a solder mask opening that exposes various bonding pads. A solder layer covers the upper and side surfaces of the bonding pads. The chip is set up on the substrate. Furthermore, a plurality of conductive bumps structurally and electrically connects the chip with various bonding pads on the substrate.
According to one embodiment of this invention, the solder layer is comprised of a low melting point solder material while the conductive bumps are comprised of a material with a higher melting point.
In this invention, a plurality of bonding pads is exposed through a large area solder mask opening within a solder mask layer fabricated using equipment having a relatively low alignment accuracy level. Hence, the production cost of the flip chip package carrier is greatly reduced. Furthermore, with a layer of low melting point solder material covering both the bonding pads and the exposed trace lines, the distance of separation between a bonding pad and its neighboring trace line can be further reduced to increase circuit and bonding pad density of the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6294840 (2001-09-01), McCormick
patent: 2001/0052647 (2001-12-01), Plepys et al.
patent: 2002/0153617 (2002-10-01), Lee
patent: 2003/0218250 (2003-11-01), Kung et al.
patent: 2004/0099961 (2004-05-01), Chu et al.
J.C. Patents
Ngo Hung V.
VIA Technologies Inc.
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