Flip-Chip interconnections using lead-free solders

Details Flip-Chip interconnections using lead-free solders Flip-Chip interconnections using lead-free solders

1996-03-12

2001-05-01

Ip, Sikyin (Department: 1742)

Metal treatment

Stock

C257S738000, C257S751000, C257S753000, C257S766000

Reexamination Certificate

active

06224690

ABSTRACT:

FIELD OF THE INVENTION
The field of the present invention is the interconnection of microelectronic circuit chips to packages, in particular the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The present invention further pertains to interconnection schemes that are environmentally acceptable because they use lead-free solder alloys and employ environmentally benign fabrication processes. Additionally, the present invention pertains to interconnection schemes that eliminate sources of soft errors in on-chip circuitry through the elimination of alpha-particle sources in the solder in contact with the microelectronics circuit.
BACKGROUND OF THE INVENTION
In the packaging of semiconductor chips, a hierarchy of interconnections is necessary. At the level of the interconnection between the chip and the substrate (or chip carrier), three different interconnection technologies are widely employed: tape automated bonding (TAB), wirebonding, and area array.
The area array is often called a flip-chip connection or C4. Since the C4 technology uses an array of solder bumps that can be placed over the entire surface area of the chip, it can achieve a higher density of input/output interconnections and better power dissipation than can wirebonding or TAB, which confine the interconnections to the chip periphery.
More specifically, the C4 technology uses solder bumps deposited on a solder-wettable layered structure known as the ball-limiting metallurgy (BLM) on the chip. After the solder pads are reflowed to form balls, they are joined to a matching footprint of solder-wettable layers on the chip carrier. It is the face-down placement of the chip on the carrier that has led C4 technology to be called flip-chip joining. Compared to other methods of interconnection, the C4 technology offers distinct advantages, including the following: 1) shorter interconnect distances, allowing faster signal response and lower inductance; 2) more uniform power and heat distribution; 3) reduced simultaneous switching noise; and 4) greater design flexibility.
Fabrication of PbSn C4 interconnections by evaporation through a metal mask has been practiced since the mid-1960s. The evaporated C4 technology has been developed and perfected since the mid-1960s as a highly reliable, high-density packaging method; it has proved extendible from the earliest products through the products of the 1990s, but the limit of extendibility to larger wafer sizes and more dense arrays has nearly been reached.
For larger wafers, evaporated C4 technology is expensive because of the high capital costs entailed in evaporators large enough to produce good deposit thickness uniformity. In addition to the capital cost, there is the cost of waste and recycling. Typically, in large evaporators, only 5% of the evaporated metal is deposited on the wafer. The rest is deposited on the evaporator wall and on the metal mask, which need to be cleaned. Also, the lead-containing waste material has to be treated as hazardous waste for recycling and disposal.
The usefulness of evaporation to produce interconnections in smaller dimensions and denser arrays is also limited by the inability to produce metal masks with sufficiently high aspect ratios and because the mismatch in the thermal expansion coefficients of the wafer and the mask causes problems. Furthermore, because of the low vapor pressure of tin, it is impossible to extend the evaporated C4 technology to the tin-based lead-free solders that are envisioned for future interconnections.
An alternative method to evaporation is electrochemical fabrication of C4s, which is a selective and efficient process. Electrochemical C4 fabrication has been reported in the literature by, for example, Yung in U.S. Pat. No. 5,162,257, which is incorporated herein by reference. These authors, however, give little attention to issues of reliability and manufacturability. Manufacturability and other integration issues of electrochemically fabricated C4s have been described by Datta, et al. in the J. Electrochem. Soc., 142, 3779 (1995), which is incorporated herein by reference. Using plating and etching processes, and through the development of sophisticated tools, it is possible to obtain a high degree of compositional and volume uniformity of electroplated solders, uniform dimensions of the ball-limiting metallurgy (BLM), and a controlled BLM edge profile.
The electrochemical process is more extendible to larger wafers and to finer C4 dimensions than the evaporated C4 technology. Electrodeposition through a photoresist mask produces solder only in the mask opening (and on any auxiliary electrodes), the deposition is highly efficient, and little waste is generated. Electrodeposition, in contrast to evaporation, is also extendible to high-tin alloys.
FIG. 1
shows a generic C4 structure and its necessary components. The electroplated C4 consists of all of the elements beginning with the ball-limiting metallurgy (hereinafter the “BLM”). The layers of the BLM provide a barrier between the device and the interconnection structure, provide for adhesion of the interconnection structure to the silicon-wafer substrate (on which the device has been fabricated), and provide a solderable layer. The materials in the BLM are chosen to be compatible with the solder alloys and with each other, to give good performance in the C4 joint, and to allow easy fabrication.
A summary of the elements comprising an electrochemically fabricated C4 and the manner in which these elements are assembled follows.
1) With reference to
FIG. 1
, the first layer to be deposited in the C4 is the adhesion/barrier layer of the BLM which provides adhesion to the underlying substrate while also preventing any interaction of the silicon wafer and its circuitry with the overlying interconnection structure. This barrier is a thin layer typically deposited by sputtering on the passivated wafer. Good barrier layers for use with lead-bearing solders are sputtered Cr or sputtered TiW, typically on the order of a thousand angstroms in thickness.
2) The next layer of the BLM is a second adhesion layer (or “glue” layer), which provides good adhesion between the barrier layer and the solderable layer. This layer may be a “phased CrCu” material consisting of co-sputtered Cr and Cu that is high in Cr at the barrier layer interface and high in Cu at the solderable metal interface. This layer is typically on the order of a thousand angstroms in thickness.
3) The final layer of the BLM is the solderable layer. The solderable layer in a typical 97Pb3Sn C4 structure is copper, typically a few thousand angstroms in thickness, deposited by sputtering.
4) The C4 pattern is defined on the wafer with an appropriate photoresist of thickness at least as great as the thickness of the solder pad to be formed.
5) The solder is electroplated through the mask.
6) After the preceding steps are completed, the photoresist is removed.
7) The BLM is formed by a combination of selective electroetching and chemical etching of the blanket metal layers.
8) The solder is reflowed. Reflow is done in a forming gas atmosphere (H
2
/N
2
) in a belt furnace or in a vacuum furnace. During reflow, the intermetallic compounds form that provide good mechanical integrity at the boundary of the solder and the solderable layer.
9) The wafer is diced into chips, which are joined to a carrier through the use of a suitable flux.
The present invention focuses on cost-effective, environmentally sound, reliable, lead-free replacements for the solders in C4 joints. The present invention also provides the enabling processes for fabrication of an integrated C4 structure, i.e., the selection of the BLM and the deposition and etching processes used to produce the final BLM structure. The current C4 technology, in order to meet the demands of the chip packaging, uses solders that are high in lead, typically 95 to 97% lead by weight. A lead-free C4 requires a solder with similar melting properties, in order to fit into the solder hierarchy.
The elimination of lead from elec

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