Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2003-06-13
2004-11-23
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S773000, C257S782000, C257S786000
Reexamination Certificate
active
06822327
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
Not applicable.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention generally relates to circuit devices of the type that are attached to a substrate with multiple solder connections. More particularly, this invention relates to conductive layers on such a device, wherein the conductive layers are configured to promote the current-carrying capability of the solder connections of the device.
(2) Description of the Related Art
Surface-mount (SM) semiconductor devices such as flip chips and ball grid arrays (BGA's) are attached to substrates with beadlike terminals formed on interconnect pads located on one surface of the device. The terminals are usually in the form of solder bumps that, after placement of the chip on the substrate, are reflowed to both secure the chip to the substrate and electrically interconnect the flip chip circuitry to a conductor pattern on the substrate. Reflow soldering techniques typically entail depositing a controlled quantity of solder on the interconnect pads using methods such as electrodeposition and printing, and then heating the solder above its melting or liquidus temperature (for eutectic and noneutectic alloys, respectively) to form a solder bump on each pad. After cooling to solidify the solder bumps, the chip is attached to the conductor pattern by registering the solder bumps with their respective conductors on the substrate, and then reheating (reflowing) the solder so as to form solder connections that are metallurgically bonded to the interconnect pads on the chip and the conductors on the substrate.
Aluminum or copper metallization is typically used in the fabrication of integrated circuits, including the interconnect pads on which the solder bumps of a flip chip are formed. Thin layers of aluminum or copper are chemically deposited on the chip surface, and then selectively etched to achieve the desired electrical interconnects on the chip. The number of metal layers used for this purpose depends on the complexity of the integrated circuit (IC), with a minimum of two metal layers typically being needed for even the most basic devices. Aluminum and its alloys are generally unsolderable and susceptible to corrosion if left exposed, and copper is readily dissolved by molten solder. Consequently, a diffusion barrier layer is required on top of copper interconnect metal, while an adhesion layer is required for aluminum interconnect metal. These layers, along with one or more additional metal layers, are deposited to form what is termed an under bump metallurgy (UBM) whose outermost layer is readily solderable, i.e., can be wetted by and will metallurgically bond with solder alloys of the type used for solder bumps.
FIGS. 1
,
2
and
3
represent, respectively, a perspective view of an IC die
110
, a perspective view of a region of the die
110
that includes a pair of solder bumps
112
, and a cross-sectional view through one of the solder bumps
112
. The solder bumps
112
are electrically connected to metal runners
114
on the die
110
through openings in a passivation layer
116
(shown only in FIG.
3
). The metal runners
114
overlie a second metal layer
118
on the die
110
, through which connections are made to the integrated circuit (not shown) on the die
110
. The portions of the runners
114
exposed through the passivation layer
116
define interconnect pads on which UBM's
120
have been deposited. As an example, the UBM
120
is represented as comprising a solderable metal (e.g., NiVCu) layer
124
deposited on an aluminum pad
122
.
As a result of die attachment, the solder bumps
112
form solder connections that carry electrical currents in and out of the die
110
, such that an inherent potential difference is established between the two ends of each bump
112
, i.e., the end attached to the die
110
and the opposite end attached to the substrate (not shown). It has been noted that, in combination with operating temperature, the electrical current through a solder bump connection can lead to a phenomenon known as “electromigration.” In its simplest form, electromigration, as it relates to the die
110
represented in
FIGS. 1 through 3
, can be defined as the separation and movement of the metallic phases within the solder bump
112
, such as the tin and lead phases within a bump
112
formed of a Sn-Pb solder alloy. In other words, the solder bump
112
, which is essentially a homogenous mixture of these phases, becomes segregated with one phase accumulating near the die
110
and the other phase accumulating near the substrate. This segregation is detrimental to the long term reliability and performance of the solder bump connection, and in some cases can lead to “electrically open” solder joints.
Flip chip solder connections used in high power applications, such as output drivers for automotive engine controllers, are particularly likely to exhibit excessive resistances and open connections associated with electromigration. It would be desirable if the reliability of these solder connections could be improved by increasing their current-carrying capability.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to improving the current-carrying capability of solder bump connections between metal layers on a surface-mount circuit device and a substrate to which the device is attached with the connections. The present invention employs a metal layer comprising at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions, such as openings defined in the pad portion, with at least some of the openings preferably extending into the leg portion.
The metal layer of this invention is adapted to carry current to and from a solder bump electrically connected to the continuous region. The multiple electrical paths split the current flow to and from the solder bump, and distribute the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where current would otherwise be concentrated. While current density can also be reduced by increasing the thickness of the metal, the present invention achieves reduced current densities without the cost of the additional metal required to increase the thickness of the metal layer. The multiple electrical paths of the metal layer can be defined in the metal layer during conventional processes undertaken to pattern the metal layer on the device surface.
Other objects and advantages of this invention will be better appreciated from the following detailed description.
REFERENCES:
patent: 3902189 (1975-08-01), Simpson
patent: 5438749 (1995-08-01), Runyon
patent: 5491364 (1996-02-01), Brandenburg et al.
patent: 6064576 (2000-05-01), Edwards et al.
patent: 6259608 (2001-07-01), Berardinelli et al.
patent: 2003/0193078 (2003-10-01), Chungpaiboonpatana et al.
U.S. patent application Ser. No. 10/075,979, Yeh et al., filed Feb. 15, 2002.
U.S. patent application Ser. No. 10/226,370, Yeh et al., filed Aug. 22, 2002.
U.S. patent application Ser. No. 10/252,502, Carter et al., filed Sep. 23, 2002.
Dikeman John M.
Gose Mark W.
Higdon William D.
Mithal Pankaj
Stepniak Frank
Chmielewski Stefan V.
Fahmy Wael
Ha Nathan W.
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