Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-12-04
2004-09-28
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S787000, C257S777000
Reexamination Certificate
active
06798044
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flip chip in a leaded molded package, and more particularly, to a flip chip in a leaded molded package with two stacked dies.
2. Description of the Prior Art
Semiconductor devices are becoming smaller and smaller. Additionally, as the need for speed, power and capacity increases, such a reduction in size leads to a contradiction in that smaller devices often have smaller capabilities.
In order to create smaller devices but with increased capabilities, the prior art has attempted to stack dies on top of one another. However, the prior art currently uses wire bonding for its interconnect scheme, which leads to higher resistance and inductance and does not allow for as thin a package as desired. Additionally, using wire bond techniques does not allow for the drain regions of a power MOSFET die to be exposed.
SUMMARY OF THE INVENTION
The present invention provides a chip device that includes a leadframe or a substrate that includes a plurality of leads. A first die is flipped onto the leadframe and the leadframe and die are then flipped together. A second die is then flipped onto the leadframe. The two dies are coupled to the leadframe with solder bumps. A molded body is placed around the dies and the leadframe such that the drain area of at least the first die is exposed.
In accordance with one aspect of the present invention, the first die is attached to the leadframe with a higher temperature reflow process while the second die is attached to the leadframe using a lower temperature reflow process.
In accordance with another aspect of the present invention, the first die of the chip device is a MOSFET while the second die is a controller IC.
Thus, the present invention provides a chip device that includes two dies stacked atop one another. The use of solder bumps allows for a small profile package. In addition, the non-use of wire bond interconnect allows for accommodating a very large size die for a given molded package body outline. A die size in excess of 150% of the nominal wire bonded package size may be accommodated by this arrangement.
Other features and advantages of the present invention will be understood upon reading and understanding the detailed description of the preferred exemplary embodiments, found hereinbelow in conjunction with reference to the drawings in which like numerals represent like elements.
REFERENCES:
patent: 5313095 (1994-05-01), Tagawa et al.
patent: 5319242 (1994-06-01), Carney et al.
patent: 5637916 (1997-06-01), Joshi
patent: 5765280 (1998-06-01), Joshi
patent: 5789809 (1998-08-01), Joshi
patent: 6075284 (2000-06-01), Choi et al.
patent: 6133634 (2000-10-01), Joshi
patent: 6184573 (2001-02-01), Pu
patent: 6225683 (2001-05-01), Yalananchiili et al.
patent: 6294403 (2001-09-01), Joshi
patent: 6303981 (2001-10-01), Moden
patent: 6313520 (2001-11-01), Yoshida et al.
patent: 6316822 (2001-11-01), Venateshwaran et al.
patent: 6380615 (2002-04-01), Park et al.
patent: 6469384 (2002-10-01), Joshi
patent: 6489678 (2002-12-01), Joshi
patent: 6566749 (2003-05-01), Joshi et al.
patent: 6627991 (2003-09-01), Joshi
patent: 6633030 (2003-10-01), Joshi
patent: 6661082 (2003-12-01), Granada et al.
patent: 6683375 (2004-01-01), Joshi et al.
patent: 2002/0066950 (2002-06-01), Joshi
patent: 2002/0066959 (2002-06-01), Joshi et al.
patent: 2002/0100962 (2002-08-01), Joshi
patent: 2002/0192935 (2002-12-01), Joshi et al.
patent: 2003/0011005 (2003-01-01), Joshi
patent: 2003/0042403 (2003-03-01), Joshi
patent: 2003/0075786 (2003-04-01), Joshi et al.
patent: 2003/0107126 (2003-06-01), Joshi
patent: 2003/0122247 (2003-07-01), Joshi
patent: 2003/0173684 (2003-09-01), Joshi et al.
patent: 2003/0197278 (2003-10-01), Joshi et al.
Joshi, et al.; U.S. pending Utility patent application No. 09/464,885; filed Dec. 16, 1999.
Clark S. V.
Fairchild Semiconductor Corporation
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