Flip chip chip-scale package

Details Flip chip chip-scale package Flip chip chip-scale package

1999-10-06

2001-07-03

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S108000, C438S118000

Reexamination Certificate

active

06255140

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor chip packages, and more particularly to a flip chip chip-scale package.
BACKGROUND OF THE INVENTION
Packaging semiconductors is a vital aspect of semiconductor manufacturing. There are many types of packaging configurations available, such as ball grid arrays (BGA), flip chip and more recently, chip-scale packages. Basically, chip-scale packages can be categorized as flex substrate, rigid substrate, lead frame and wafer-level assembly. In the categories of flex substrate and rigid substrate, both flip chip and wire bonding technologies may be used.
Flip chip packages are quite fragile and require careful assembly and handling techniques. Chip-scale packages are being developed to combine the high density of the BGA packages and the small size of the flip chip packages. The chip-scale package need only be slightly larger than the bare chip.
An example of a packaging technique for a conventional flip chip chip-scale package (CSP) is shown in FIG.
1
. In the flip chip CSP, a semiconductor die
101
is first mounted to the top surface of a substrate
102
using flip chip technique. An under fill region
103
is then formed below the die and at an outer circumferential surface of the solder balls
104
formed on the surface of the die
101
. In the chip-scale package, solder balls
104
are attached to I,O pads on the surface of the substrate
102
.
The packaging technique shown in
FIG. 1
has some disadvantages. One is that chips are subject to damage because they are exposed during packaging steps. Another problem is that an external heat sink can not be easily attached to the die for high-power chip packages.
Another example of a conventional packaging technique is shown in
FIG. 2
, which illustrates the final assembly process of a Mitsubishi CSP. In the final assembly process, four general steps are taken. They are steps of inner bump bonding, encapsulation, base frame separation, and solder ball attachment. At the step of inner bump bonding, the inner bumps
211
are first formed on a base frame
212
. The chip is then over-molded with an encapsulating material for protection. External electrode bumps
241
are formed and directly bonded to the bond pads after the inner bumps are separated from the base frame
212
. The electrode bumps serve as the external electrodes for surface mounting on a printed circuit board.
The CSP final assembly process shown in
FIG. 2
also has some disadvantages. One is forming the inner bumps is a complicate process. Another problem is chips are not easy to be cooled off due to the externally molded plastic protection.
SUMMARY OF THE INVENTION
This invention has been made to overcome the above mentioned drawbacks for flip chip chip-scale packages. It is an object of the present invention to provide a flip chip chip-scale package with a metal heat slug overlaying the surface of a semiconductor chip. By having an externally attached heat slug, the hardness and the strength of the chip package is improved. The chip-scale package of the invention protects chips from being cracked. It also makes the heat of the chip dissipating faster so that the chip may cool faster. This invention also enhances electrical shielding for the chips. In the mean time, it reduces electromagnetic interference for the chips.
Another object of the invention is to provide a packaging process in which current standard integrated circuit packaging equipment may be used. Using the standard packaging equipment eliminates the high cost associated with purchasing specialized manufacturing equipment. The packaging technique of the invention is simple enough that automatic manufacturing of chip-scale packages is also achievable. In the mean time, the packaging process allows an external heat sink to be attached easily.
In a first embodiment of the flip chip chip-scale package of this invention, a heat slug overlays on the upper surface of a CSP. Adhesive epoxy is directly applied between the inner surface of the heat slug and the top surface of the die for bonding the heat slug and the die together. In this manner, the heat slug serves as a protection device as well as a heat dissipation sink.
In a second embodiment of the flip chip chip-scale package of this invention, a portion of the heat slug is removed. The adhesive epoxy that bonds the heat slug to the die is only applied to the edge of the upper surface of the die. In this embodiment, because the semiconductor chip is not fully covered by the heat slug, heat may be better dissipated.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from a careful reading of a detailed description provided herein below, with appropriate reference to the accompanying drawings.


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patent: 5510956 (1996-04-01), Suzuki
patent: 5672548 (1997-09-01), Culnane et al.
patent: 5789810 (1998-08-01), Gross et al.
patent: 5805422 (1998-09-01), Otake et al.
patent: 5866943 (1999-02-01), Mertol
patent: 5898224 (1999-04-01), Akram
patent: 5905636 (1999-05-01), Baska et al.
patent: 5909056 (1999-06-01), Mertol
patent: 5909057 (1999-06-01), McCormick et al.
patent: 6008536 (1999-12-01), Mertol
patent: 6069023 (2000-05-01), Bernier et al.

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