Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1998-07-22
2002-09-10
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S778000, C438S678000, C427S123000, C427S124000, C427S097100, C205S123000
Reexamination Certificate
active
06448644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuit assemblies, and in particular, to the electrical connection of integrated circuits to substrate circuitry, printed circuit board, and interconnect components. Most specifically, the invention relates to a flip chip assembly which includes a single or multi-layered substrate in which via holes are electrically and mechanically connected to the input/output terminal pads of the integrated circuits through direct metallization.
2. Related Art
Recent developments of semiconductor packaging suggest an increasingly critical role of the technology. New demands are coming from requirements for more leads per chip and hence smaller input/output terminal pad pitch, shrinking die and package footprints, and higher operational frequencies that generate more heat, thus requiring advanced heat dissipation designs. In addition to these demands, the more stringent electrical requirements must not be compromised by the packaging. All of these considerations must be met and, as usual, placed in addition to the cost that packaging adds to the semiconductor-manufacturing food chain.
Conventionally, there are three predominant chip-level connection technologies in use for integrated circuits, namely wire bonding, tape automated bonding (TAB) and flip chip (FC) to electrically or mechanically connect integrated circuits to leadframe or substrate circuitry. Wire bonding has been by far the most broadly applied technique in the semiconductor industry because of its maturity and cost effectiveness. However, this process can be performed only one wire bond at a time between semiconductor chip's bonding pads and the appropriate interconnect points. Furthermore, because of the ever increasing operational frequency of the device, the length of the interconnects needs to be shorter to minimize inductive noise in power and ground, and also to minimize cross-talk between the signal leads. An example of such a method is disclosed in U.S. Pat. No. 5,397,921 to Karnezos.
Flip chip technology involves mounting of an unpackaged semiconductor chip with the active side facing down to an interconnect substrate through contact anchors such as solder, gold or organic conductive adhesive bumps. The major advantage of flip chip technology is the short interconnects which, therefore, can handle high speed or high frequency signals. There are essentially no parasitic elements such as inductance. Not only is the signal propagation delay slashed, but much of the waveform distortion is also eliminated. Flip chip also allows an area array interconnecting layout that provides more I/O than a perimeter interconnect with the same die size. Furthermore, it requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space is used. An example of such a method is disclosed in U.S. Pat. No. 5,261,593 to Casson et al.
FIG. 1
is a schematic cross-sectional view of a prior art flip chip assembly in which an integrated circuit chip
101
is attached to a substrate
102
through electrically conductive bumps
103
. These bumps
103
make electrical connection between bond pads
104
formed on the chip
101
and specific one of the conductive traces
105
formed on the surface of the substrate
102
. These traces
105
further extend to the other side of the substrate
103
through via holes
107
that are formed within the substrate
102
. In the dielectric substrate, a via hole connects two or multiple layers of circuitry in a substrate. It can link both sides of the finished substrate, whereas a blind via link one side to one or multiple internal layers and a buried via links internal layers without being visible on the surface of the board. These via holes are typically metallized on the sidewall with copper by electroless plating and electroplating. Underfilled material
106
is typically applied between integrated circuit chip
101
and substrate
102
in order to reduce the stress due to thermal characteristic mismatch of the chip
101
and substrate
102
. Conductive traces
105
formed on the top of the substrate
102
extend from the via holes to specific contacting pads or balls
108
and therefore connect to the external circuitry.
While flip chip technology has tremendous advantages over wire bonding, its cost and technical limitations are significant. First of all, flip chip technology must confront the challenge of forming protruded contact anchors or bumps to serve as electrical connections between the integrated circuit chip and substrate circuitry. A variety of bumping processes have therefore been developed. These include a vacuum deposition of an intermediate under-bump layer which serves as an adhesive and diffusion barrier. This barrier layer is composed of a film stack which can be in the structure of chromium/copper/gold. Bumping materials such as solder are subsequently deposited onto this intermediate layer through evaporation, sputtering, electroplating, solder jetting or paste printing methods followed by a reflow step to form the solder contacts.
Techniques for fabricating the intermediate under-bump barrier layer as well as the bump material utilizing electroless plating are also known. In these attempts, as shown in
FIG. 2
, the input/output terminal pads
201
of the integrated circuit chip
200
are firstly activated/by a catalytic solution which will selectively activate the pad material through chemical reactions and form a thin layer of catalyst
202
. This thin layer of catalyst
202
is typically composed of zinc or palladium. When electroless plating is executed thereafter, material such as nickel, gold, palladium or their alloys can be selectively initiated and continuously deposited on the pads to form the bumps
203
. In the above-described electroless plating process, hypophosphate or boron hydride are commonly used as the reducing agent in the nickel plating solution. This electroless plated bump not only provides the protruding contact anchor but also serves as the diffusion barrier and sealing. Contacting material such as solder, conductive adhesive or polymer is subsequently applied onto these bumps by techniques such as solder dipping, solder jetting, evaporation, screen printing or dispensing. An example of such a method is described in the U.S. Pat. No. 5,583,073, to Lin et al.
Although the electroless technique provides an economical, simple and effective method for fabricating the under bump barrier layer, contacting material such as solder or adhesive is still required for assembling. Solder dipping or screen printing of solder paste onto these bumps has been explored but with very limited success due to solder bridging and non-uniform deposition of solder on the metal bumps. This process also; it suffers from poor process control as the input/output terminal pad spacing gets smaller. Additional problems have been encountered with tin/lead solder due to its increase in electrical resistance over time. Moreover, the solder contacts are easily fatigued by mechanical stressing.
Organic contacts which utilize conductive adhesive to replace solder joint is also described by U.S. Pat. No. 5,627,405, to Chillara. Generally speaking, the conductive adhesive, which is made by adding conductive fillers to polymer binders, holds a number of technical advantages over soldering such as environmental compatibility, lower-temperature processing capability, fine pitch and simplified processes. However, conducive adhesive does not normally form the metallurgical interface in the classical sense. The basic electrical pathway is through conductive particles of the adhesive that are in contact with one another and reach out to the two contact surfaces of the components. Under certain environments, this interconnect system may cause problems because the penetration of moisture through the polymer may induce corrosion and oxidation of the conducting metal particles which results in unstable electrical contacts. Furthermore, fail
Sigmond David M.
Wilczewski Mary
LandOfFree
Flip chip assembly with via interconnection does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flip chip assembly with via interconnection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip chip assembly with via interconnection will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2826082