Flicker reduction circuit for interlaced video images

Details Flicker reduction circuit for interlaced video images Flicker reduction circuit for interlaced video images

1991-02-01

1993-01-26

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 11, 358166, H04N 701

Patent

active

051826437

ABSTRACT:
Adjacent lines of non-interlaced horizontal input video signal are buffered and combined using time division multiplexing on a pixel by pixel basis to produce an interlaced digital output signal. This time division multiplexed output signal is suitable for mapping through a color look-up table and subsequent digital to analog conversion to an interlaced analog output video signal. The image produced when this analog output signal is displayed on a video output device will have reduced apparent flicker.

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patent: 4723163 (1988-02-01), Skinner
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