Flicker reduction apparatus

Details Flicker reduction apparatus Flicker reduction apparatus

1989-10-11

1991-02-26

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358140, 358166, H04N 506, H04N 300

Patent

active

049965956

ABSTRACT:
Intermediate vertical synchronizing signals are generated to occur between the vertical synchronizing signals normally included in a conventional video signal. A first counter counts clock signals which are synchronized with the horizontal synchronizing signals normally included in the conventional video signal to provide a count representing the number of clock signals which are present in one-half of a field interval of that conventional video signal. The count provided by the first counter during the second preceding field interval is temporarily stored and compared to a count produced by a second counter which counts the clock signals from the beginning of the field interval. An intermediate vertical synchronizing signal is generated when the count of the second counter is equal to the stored count.

REFERENCES:
patent: 4524387 (1985-06-01), Tamer
patent: 4616260 (1986-10-01), Erwin
patent: 4617594 (1986-10-01), Katagiri
patent: 4668974 (1987-05-01), Kita
patent: 4800429 (1989-01-01), Perkins

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