Flicker reduction and size adjustment for video controller with

Details Flicker reduction and size adjustment for video controller with Flicker reduction and size adjustment for video controller with

1994-09-30

1996-04-23

Metjahic, Safet

Television

Format conversion

Progressive to interlace

348441, 348447, H04N 701

Patent

active

055108431

ABSTRACT:
An apparatus and method are provided for reducing flicker and/or vertically scaling an interlaced video image. In a first embodiment, a sequence controller selectively addresses a video memory to retrieve pixel data from adjacent scan lines. The pixel data is multiplexed and converted into RGB data in a look up table and stored in upper and lower latches as upper and lower pixel data. The upper and lower pixel data is then weighted using a predetermined weighting scheme to produce hybrid pixel color data for an even or odd field. By reducing relative contrast between even and odd field lines, flicker is reduced. In a second embodiment, vertical resolution is reduced, for example, from 480 lines to 400 lines, by applying a series of weighting schemes or filters to weight data from six input lines into five output lines. To reduce flicker in the output lines, data from adjacent lines may weighted to reduce relative contrast. Due to the 6:5 reduction, a discontinuity in the output lines may exist where adjacent line data is not weighted. Luminance data from a third adjacent line may be weighted with pixel data from adjacent lines to reduce flicker at the discontinuity.

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