Television – Format conversion – Field rate type flicker compensating
Reexamination Certificate
1997-12-11
2001-11-20
Lee, Michael (Department: 2614)
Television
Format conversion
Field rate type flicker compensating
C708S301000, C708S319000, C348S910000, C382S260000
Reexamination Certificate
active
06320619
ABSTRACT:
BACKGROUND
1. Field
The present invention relates to displaying personal computer (PC) graphics on a television (TV) screen and, more particularly, to a flicker filter circuit for filtering the PC signals.
2. Background Information
Displaying personal computer (PC) graphics content on a television (TV) screen is desirable to enable multimedia PCs to become a common feature in most households as an entertainment appliance. To generate TV signals with acceptable quality, it is desirable to employ a flicker filter and also overscan compensation to convert high resolution non-interlaced video graphics adapter (VGA) signals into low resolution, interlaced TV signals in formats such as National Television Standard Committee (NTSC), Phase Alternation Line (PAL) or Sequential Color with Memory (SELAM). In this context, a flicker filter refers to a digital signal sample filter to filter digital signal samples for a progressive video frame so that when the frame is displayed on an interlaced video display system, flicker is not perceived by a user. In this context, overscan compensation refers to processing digital signal samples from a non-interlaced system so that a frame visible on a non-interlaced system is visible on an interlaced system, although an interlaced system does not permit the borders of the frame to be seen.
Typically, a flicker filter comprises a vertical low-pass filter which may be used to down scale digital video signals. The term vertical in this context refers to the filtering of parallel lines of digital signal samples or pixels, such as in a video frame, for example. The quality of flicker reduction depends, at least in part, on the filter size. A three-tap flicker filter typically produces marginally acceptable quality signals. Likewise, a 4- to 5-tap flicker filter would typically produce a higher quality signal. In a conventional filter design, to implement an N-tap flicker filter, N being a positive integer greater than one, N−1 lines of digital video signals or digital signal samples are typically stored, such as in line buffers. Further, down scaling with a non-integer ratio, such as for overacan compensation, typically involves additional line buffers as well. Unfortunately, the size and number of line buffers is a cost factor when implementing a flicker filter circuit, such as in a graphics controller chip, for example. Typically, a line buffer employs large numbers of transistors or gates and this increases costs. A need, therefore, exists for a circuit configuration or technique for implementing a flicker filter circuit that reduces the number of transistors or gates employed.
SUMMARY
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a flicker filter circuit. The flicker filter circuit has a configuration so that during filter operation two line buffers are employed to store partial sums of the filtered input digital signal samples.
Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: three line buffers, three multipliers, and three adders. The buffers, multipliers and adders are coupled in a circuit configuration so as to implement a flicker filter during circuit operation.
REFERENCES:
patent: 4709343 (1987-11-01), Van Cang
patent: 5455628 (1995-10-01), Bishop
patent: 5742349 (1998-04-01), Choi et al.
patent: 5990965 (1999-11-01), Herz et al.
patent: 6061094 (2000-05-01), Maietta
Intel Corporation
Lee Michael
Skaist Howard A.
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