Flicker elimination system

Television – Format conversion – Field rate type flicker compensating

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Details

348448, 348457, 348443, H04N 701, H04N 1120

Patent

active

058446192

ABSTRACT:
A system and method for eliminating flicker in an interlaced video-display image using an input-video processor, a feature-video processor, a frame buffer, an RGB-output processor, an output-video processor, a control processor, and a synchronized-clock doubler. An input video signal is processed as processed component video information and written to a video memory at a horizontal-scan rate and a vertical-scan rate. Based on the input video signal, a vertical-scan synchronization pulse and a horizontal-scan synchronization pulse are generated and then harmonically doubled. The processed component video information is read from the video memory, responsive to the harmonically doubled synchronization pulses, at a harmonically doubled horizontal-scan rate and a harmonically doubled vertical-scan rate, reading in an interlaced format, with each frame being contiguously read twice in a proper odd-even order as when normally read to generate four fields of video information per frame which may be interlaced. The result is a video display image having improved visual characteristics which is harmonic to any one of NTSC, PAL and SECAM broadcast standards.

REFERENCES:
patent: 4322750 (1982-03-01), Lord et al.
patent: 4701793 (1987-10-01), den Hollander et al.
patent: 4851908 (1989-07-01), Welles et al.
patent: 5469217 (1995-11-01), Ibental et al.
patent: 5627598 (1997-05-01), Tsuchida

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