Flexibly suspended heat exchange head for a DUT

Details Flexibly suspended heat exchange head for a DUT Flexibly suspended heat exchange head for a DUT

1998-06-22

2002-05-21

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S761010, C324S754090, C324S1540PB

Reexamination Certificate

active

06392431

ABSTRACT:

The present invention relates broadly to the field of integrated circuit (IC) or chip manufacture and use and particularly to a device for precisely controlling and measuring the temperature of a device under test (DUT).
During manufacture by the chip maker, chips typically undergo three separate test cycles: (1) in-process testing, such as continuous monitoring of sheet resistivities, junction depths, and other pertinent device parameters, such as current gain and voltage breakdown; (2) a preliminary electrical testing called burn-in; and (3) a detailed final testing for reliability and performance to grade or sort the chips. The present invention relates to improvements in the last type of testing.
The final testing of chips is one of the more expensive and time consuming stages of the manufacturing process. Automatic high speed testing is practically mandatory to the final testing of modern chips because a large number of complex tests are required to check even the simplest types of circuits.
After burn-in, it is conventional for the chips to undergo a number of functional tests to evaluate their performance. One by one, each chip is subjected to a series of long and short functional tests. The number and complexity of these functional tests varies from chip maker to chip maker. Long functional testing of digital memory chips generally involves the pattern testing of each chip on an individual basis. Commonly used routines are checkerboard patterns of 1s and 0s or floating of a 1 or 0 from cell to cell while the adjacent cells are maintained in the opposite state. For larger memories, the generation of these test patterns requires a larger number of functional tests. Generally, the time required for adequate pattern testing increases at a rate which is proportional to the square of the number of bits of storage in the digital memory chip. As the bit storage capacity of a digital memory chip increases, the time required for adequate pattern testing increases at an exponential rate.
Short functional testing of chips involves the testing of each chip on an individual basis to determine whether it meets the specs set down in the data sheet, e.g. operating speed, and voltage and current parameters. These so-called short functional tests generally require much less testing time than pattern testing. Both the long and short functional tests have heretofore been performed by chip makers in various sequences and at various temperature levels. After the functional tests are completed, the chips that have satisfactorily undergone all tests are subjected to quality control testing.
In this third stage, the functional tests are designed to test the chips at a constant temperature, usually the junction temperature. For chips with low power dissipation, eg <1 watt, maintaining the temperature constant by convection, flowing a fluid (air stream) across a DUT surface, is usually sufficient.
As transistor densities and counts (per chip) continue to increase, the power dissipation (P
D
) of a chip increases markedly. P
D
also increases, proportionately, with increasing clock rate (for the common CMOS devices). The vast majority of digital systems change their internal states in synchronism with a square wave or clock signal common to the entire chip. Performance or useful work performed by a chip per time (R), is usually directly proportional to the clock rate or frequency. Current and proposed design P
D
's are becoming prohibitive (the chips are getting too hot). Chips are designed to operate in highly temperature variable environments. The heat generated by a chip affects its temperature and thus feedback exists. It is always desirable to operate the chip at a constant internal temperature (junction temperature). Typically, this internal temperature is set to be less than the maximum allowable to allow for the violability and power consumption goals of the chip design. With the testing of the current and the expected proposed chip designs, the total heat impinging on the chip increases significantly (due either to external temperature increases or to increases in the system clock frequency).
When a chip is performance tested at its maximum capacity and maximum system clock frequency, it is necessary to control the ambient temperature to maintain the junction temperature of the chip constant in order to provide a reliable frame of reference or standard against which each chip is tested. When a chip is tested, it is referred to as a device under test (DUT).
Therefore, as the ability of chip manufacturers to reduce the physical size of chips has improved, the power dissipation in the chips so manufactured has accordingly increased. As a result, when the DUTs are tested, it has become increasingly necessary to provide some form of cooling to maintain the DUT at a constant temperature, usually its junction temperature.
Generally, the prior art systems are not capable of precisely controlling the DUT temperatures at >3-5 watts of power dissipation.
Presently, there are two major problems in precisely controlling the temperature of a DUT. In the third stage of testing as described above, the power dissipation inherent in current chips (and future chips) is high. The corresponding heat generated must be removed substantially simultaneously (heat sink). In correlation with the rapid heat removal is the requirement of precise monitoring and control of the DUT temperature at the desired test temperature.
Therefore, one major problem faced is to establish a superior heat transfer relationship between the DUT and a heat exchange module which engages the DUT.
The other manor problem is to measure and control the temperature of the DUT. With regard to this latter problem, various approaches are known in the prior art for measuring heat flow. One such approach is illustrated in U.S. Pat. No. 3,720,103 which relates to a heat flux meter. In that device, thermocouples are used to measure the temperature difference between two surfaces. The sensed temperature difference controls a heater which is adjusted so that heat flow between the surfaces is prevented. The first surface is shielded from the environment to prevent heat flow therefrom to this surface. This device, however, is not suitable for measuring the performance of a cooling device such as a heat sink or heat transfer device used in a semiconductor module for cooling a semiconductor chip or the like.
Another method is illustrated in U.S. Pat. No. 3,745,460. In this approach, a current pulse is fed into the semiconductor causing heat to be generated therein. The detected time interval between cessation of the pulse and detection of maximum heat transfer leads to a determination of the thermal resistance.
A further method is described in U.S. Pat. No. 4,396,300. The apparatus includes an electric heater for heating a block which surrounds and engages part of the tube. A liquid is pumped through the tube and a thermistor is used to measure the fluid temperature. A pressure drop sensor is provided to sense the drop in pressure across the block. The sensed data is transferred to a computer for computing the heat transfer resistance. Like the other approaches mentioned above, this method too is not suitable for determining the effectiveness of a heat transfer device used in a module to cool a DUT.
However, these other problems of accurate and effective temperature control of a DUT during ‘burn in’ were overcome in my earlier issued U.S. Pat. Nos. 5,126,656; 5,164,661; 5,315,240 and PCT Publication WO94/22029 which are hereby incorporated by reference in their entireties into this disclosure. That is, my earlier work and inventions for the control and measurement of a DUT during ‘burn in’ are applicable to the control and measurement of the temperature of a DUT during the functional testing (third stage) of a DUT.
The present invention overcomes the one major problem heretofore described and is directed to a device which establishes a superior heat-transfer relationship between a DUT and a heat-exchange device. Although the invention will be

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