Flexible VLSI on-chip maintenance and test system with unit I/O

Details Flexible VLSI on-chip maintenance and test system with unit I/O Flexible VLSI on-chip maintenance and test system with unit I/O

1987-10-23

1990-03-27

Atkinson, Charles E.

Excavating

371 223, G01R 3128

Patent

active

049127098

ABSTRACT:
This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.

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patent: 4701916 (1987-10-01), Naven et al.
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Konemann, et al., Built-In Test for Complex Digital Integrated Circuits, Fifth European Solid State Circuits Conference, ESSCIRC 79, Southampton, England, Sep. 18-21, 1979, pp. 89-90.
Zobniw, Production Signature Analysis with Relaxed Design Constraints, IBM Tech. Discl. Bulletin, vol. 24, No. 7A, Dec. 1981, pp. 3323-3327.
Hanson, III, High Speed Signature Analysis, IBM Tech. Discl. Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 974-975.

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