Flexible utilization of general flip-flops in programmable array

Details Flexible utilization of general flip-flops in programmable array Flexible utilization of general flip-flops in programmable array

1991-02-08

1992-05-26

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 3072722, H03K 19177

Patent

active

051171325

ABSTRACT:
A programmable array logic unit (PAL) having a disconnected array of gates, inverters and D-Type flip-flops, is utilized by burning-in the interconnections, to enable the D flip-flops to function as J-K flip-flops and/or toggle flip-flops to enable flexibility in the functions available for utilization, by providing inputs for Direct Set, Direct Clear and Hold.

REFERENCES:
patent: 4789951 (1988-12-01), Birkner et al.
patent: 4879481 (1989-11-01), Pathak et al.
patent: 4912345 (1990-03-01), Steele et al.

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