Flexible translation storage buffers for virtual address transla

Details Flexible translation storage buffers for virtual address transla Flexible translation storage buffers for virtual address transla

1997-06-26

1999-05-04

Kulik, Paul

Data processing: database and file management or data structures

Database design

Data structure types

711202, 711203, 711206, 711207, 711212, 711118, G06F 1208

Patent

active

058999949

ABSTRACT:
A technique for managing address translation storage buffers (TSBs) supports multiple pools of different TSB sizes and dynamically assigns a process to its own TSB of the proper size as the needs of the process change. A process is assigned a small TSB and the system migrates the process to a larger TSB if needed. One method includes the steps of identifying sizes of TSBs to support, allocating a TSB pool in memory with these sizes, selecting an appropriately sized TSB for a process, and migrating that process to a larger size should the process require more memory. A second method allocates a TSB pool by determining an appropriate size for the TSB pool, determining sizes of TSBs to support, allocating memory for the pool and initializing status block for each size of TSB. A third method selects an appropriate TSB for a process by selecting a smallest supported size of a TSB from the pool. A fourth method migrates a process to a larger size by determining whether the current TSB is of an inappropriate size, selecting a larger TSB size, invalidating the previous TSB, and selecting a TSB of the new size from the TSB pool. Variations on these methods require that the memory spaces shared by the TSBs of different sizes are coexistent, require that the TSBs be stored in virtual space or that entries in the translation look-aside buffer (TLB) be reserved for a separate user TSB and kernel (system) TSB.

REFERENCES:
patent: 4376297 (1983-03-01), Anderson et al.
patent: 5479627 (1995-12-01), Khalidi et al.
Madhusudhan Talluri et al., "Tradeoffs in Supporting Two Page Sizes," May 1992, Computer Architecture News, vol. 20, No. 2, pp. 415-424.

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