Flexible synthesizer for multiplying a clock by a rational...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

Reexamination Certificate

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Details

C331S016000, C331S025000, C327S156000

Reexamination Certificate

active

07026878

ABSTRACT:
A frequency synthesizer that includes two fractional dividers, two noise-shaped quantizers, three integer dividers, a PLL, an algorithm embodied in control logic, and an adjustment means. The noise-shaped quantizers are used to quantize two fractional (fixed-point) values, derived from the divider control words, into time-varying values. The dividers and PLL are used to generate an output signal by means of multiplying a reference signal by the quotient of the divider control word values. Accordingly, the frequency synthesizer of the present invention can provide a very precise output clock, with the average output frequency being the input frequency multiplied by the quotient of the two divider control words, and with high jitter stability.

REFERENCES:
patent: 2004/0032898 (2004-02-01), Smith
patent: 2004/0036509 (2004-02-01), Smith
patent: 2004/0052324 (2004-03-01), Smith
patent: 2005/0046491 (2005-03-01), Smith

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