Flexible SPDIF verification tool

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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Details

C703S019000

Reexamination Certificate

active

07409329

ABSTRACT:
A system and method of verifying the format of a simulated signal produced during the simulation of an electronic circuit is disclosed. One aspect of the present invention includes a method of extracting timing information from a single simulated serial digital audio signal that comprises both data and clock. An embodiment of the present invention may verify operation of the simulated electronic circuit by setting the value of a first simulated signal according to predetermined events that occur in a second simulated signal. The second simulated signal may be parsed using timing information extracted from the second simulated signal, and the format of the second simulated signal may be matched against a predetermined format based upon the results of the parsing. An embodiment of the present invention may, for example, be employed during software simulation to verify the operation of exemplary devices such as application specific circuits (ASICs) used in the generation of signals meeting the Sony/Philips Digital Interconnect Format (SPDIF).

REFERENCES:
patent: 5535223 (1996-07-01), Horstmann et al.
patent: 6185726 (2001-02-01), Chou
patent: 6578181 (2003-06-01), Hisada et al.
patent: 7079997 (2006-07-01), Hsu et al.
patent: 2001/0033629 (2001-10-01), Ito

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