Flexible semiconductor interconnect fabricated by backside...

Details Flexible semiconductor interconnect fabricated by backside... Flexible semiconductor interconnect fabricated by backside...

2001-01-08

2001-06-05

Brown, Glenn W. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S760020, C324S765010, C324S755090, C324S758010, C029S874000, C029S876000

Reexamination Certificate

active

06242931

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor testing and specifically to an improved interconnect for electrically testing semiconductor components such as dice, packages, wafers, panels, boards, and electronic assemblies containing dice or packages.
BACKGROUND OF THE INVENTION
Different types of semiconductor components are tested following the fabrication process. Test systems have been developed for handling the components, and for applying test signals to the integrated circuits, and other electrical elements, contained on the components. For example, discrete semiconductor components, such as bare dice and chip scale packages, are tested at the die level using carriers designed to temporarily package one or more components. Semiconductor or wafers containing multiple dice or multiple chip scale packages, are tested using wafer level systems, such as wafer probers. Other electronic assemblies containing semiconductor dice or packages, such as circuit boards, and field emission displays, are also tested following fabrication.
The components include terminal contacts which provide electrical connection points for applying the test signals. For example, bare dice and semiconductor wafers typically include bond pads which function as terminal contacts. Chip scale packages typically include solder balls, which function as terminal contacts. Electronic assemblies, such as circuit boards and field emission displays, can include test pads, which function as terminal contacts.
The test systems include an interconnect that makes the temporary electrical connections with the terminal contacts on the components. Depending on the system, the interconnect can be die sized, or wafer sized. U.S. Pat. No. 5,686,317 entitled “Method For Forming An Interconnect Having A Penetration Limited Contact Structure For Establishing A Temporary Electrical Connection With A Semiconductor Die”, describes a die level interconnect configured for use with a carrier. U.S. Pat. No. 5,869,974 entitled “Micromachined Probe Card Having Compliant Contact Members For Testing Semiconductor Wafers”, describes a wafer level interconnect configured for use with a wafer prober.
One material that can be used to fabricate interconnects is silicon. Silicon is used as a substrate material and also to form contacts for the interconnect. With silicon, a coefficient of thermal expansion (CTE) of the interconnect matches the CTE of the component. This minimizes thermal stresses during test procedures, such as burn-in, which are conducted at elevated temperatures.
One aspect of silicon is that it is a relatively rigid material that does not easily flex to accommodate differences in the planarity of the contacts on the components. Accordingly, silicon interconnects require relatively large biasing forces to permit the interconnect contacts to engage the component contacts. Often times the component, rather than the interconnect, will flex under the large forces applied during test procedures. However, in order to minimize the possibility of damage to components, it is preferable that the components not be overloaded, or stressed, during a test procedure.
Sometimes the interconnect contacts, are designed to flex to accommodate variations in the planarity, or z-direction location, of the terminal contacts on the components. However, this can make the interconnect more complicated and less reliable, and may require relatively complicated fabrication processes. The present invention is directed to an interconnect which is thinned to provide a flexible structure for engaging semiconductor components.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved interconnect for testing semiconductor components, and a method for fabricating the interconnect are provided. The interconnect comprises a thinned substrate, and a pattern of contacts on the substrate configured to electrically engage contacts on the components. In illustrative embodiments the substrate comprises silicon, but alternately can comprise ceramic, plastic, another semiconductor material such as germanium, or a composite material such as silicon-on-glass, or silicon-on-sapphire.
The interconnect can be configured for die level testing of discrete components, such as bare dice or chip scale packages, or alternately for wafer level testing of multiple components contained on a common substrate, such as a wafer, a panel, a circuit board, or an electronic assembly. In addition, the interconnect contacts can be configured to electrically engage either planar component contacts (e.g., bond pads, test pads, land pads), or bumped component contacts (e.g., solder balls, metal bumps, conductive polymer bumps). For engaging planar contacts, the interconnect contacts comprise etched members with projections for penetrating the planar contacts to a limited penetration depth. For engaging bumped contacts, the interconnect contacts comprise projections configured to penetrate the bumped contacts, or alternately recesses sized and shaped to retain the bumped contacts.
The method for fabricating the interconnect includes the steps of: providing a substrate, forming interconnect contacts on a circuit side of the substrate, covering the circuit side with a protective mask, thinning a backside of the substrate, and then removing the protective mask. The mask protects the interconnect contacts during the thinning step. In addition, the mask provides a planar surface for mounting the interconnect to a chuck, or similar tool, for thinning. Prior to removing the mask, additional fabrication process steps such as via formation, metallization, and dicing can be performed on the interconnect while the mask remains in place. Also, rather than removing all of the protective mask following the fabrication process, selected portions of the mask can be removed while other portions remain. In this case, the remaining portions of the mask can be configured to provide permanent structures on the interconnect, such as alignment fences, support structures, insulating layers, protective layers, and molding dams.
The protective mask can comprise any protective material suitable for covering the interconnect contacts and providing a planar surface. Exemplary protective materials include curable polymers, such as epoxy and silicone. Alternately the protective material can comprise a film material, such as polyimide tape.
In an illustrative embodiment, the protective mask comprises a photoimageable polymer material, such as a thick film resist, which is blanket deposited on the substrate by spin on or other process, developed, planarized, if necessary, and then cured as required. The thinning step can be performed by chemically mechanically planarizing or grinding a backside of the substrate, or alternately by etching the backside of the substrate. During the thinning step, the protective mask protects the interconnect contacts, strengthens the substrate, and provides a planar surface for handling. Preferably, the fabrication process is performed on a wafer of material, which following removal of the protective mask, can be singulated into individual interconnects.
Following the fabrication process, the thinned interconnect can be mounted to a rigid substrate using a compliant polymer layer. During a test procedure using the interconnect, the thinned substrate can flex with the compliant layer upon application of a biasing force, while the component remains relatively planar. This flexibility permits the interconnect contacts to electrically engage the component contacts even with variations in the dimensions and planarity of the component contacts.
For a die level test system, the interconnect is configured for assembly in a testing apparatus, such as a carrier, configured to retain one or more components in electrical communication with testing circuitry. The testing apparatus includes a base on which the interconnect is mounted, and a force applying mechanism for biasing the components against the interconnect. For a wafer level test system, the interconne

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