Flexible SDRAM clocking (MS-DLL)

Details Flexible SDRAM clocking (MS-DLL) Flexible SDRAM clocking (MS-DLL)

2007-02-20

2007-02-20

Tran, Michael (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

11032604

ABSTRACT:
A delay lock loop for use in meeting SDRAM timing requirements, wherein a timing relationship between data generated by a computer chip and a clock in said DRAM is fully programmable, and wherein said delay lock loop is digitally implemented. The delay lock loop includes a first delay chain to measure a number of delay taps in a single clock cycle of the clock of the SDRAM and a second delay chain to delay the clock of the SDRAM. The second delay chain is matched to the first delay chain.

REFERENCES:
patent: 6492852 (2002-12-01), Fiscus
patent: 6664830 (2003-12-01), Miller
patent: 6895522 (2005-05-01), Johnson et al.
patent: 2002/0130691 (2002-09-01), Silvestri
patent: 2004/0008714 (2004-01-01), Jones
patent: 2005/0138457 (2005-06-01), Gomm et al.

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