Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2002-04-29
2003-05-13
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000
Reexamination Certificate
active
06563448
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of wireless telephony, and is more specifically directed to audio output from multiple digital sources by way of a wireless telephone handset.
As is well-known in the art, digital modulation techniques have greatly improved the audio fidelity and transmission range of wireless telephones, while also significantly reducing the cost of service. Of course, the digital wireless telephone must demodulate and decode the incoming digital signal, and convert it into analog form to drive the audio speaker with a conventional audio signal. Accordingly, modem wireless telephones include a digital-to-analog converter (DAC) for performing this function.
A well-known DAC architecture is referred to as the oversampling &Sgr;&Dgr; (“sigma-delta”) DAC. A fundamental example of the oversampling &Sgr;&Dgr; DAC is described in Naus et al., “A CMOS Stereo 16-bit D/A Converter for Digital Audio,”
Journal of Solid-State Circuits,
VO. SC-22, No. 3 (IEEE, June 1987), pp. 390-395. According to this approach, the incoming digital data stream is oversampled by a significant multiple (e.g., 256 times the CD sample data rate of 44.1 kHz), and modulated into a one-bit data stream by a sigma-delta modulator. This one-bit data stream is applied to a 1-bit DAC that modulates a DC voltage with the one bit data stream to produce the output analog signal. In conventional DACs of this type, the sigma-delta modulator and the 1-bit DAC each operate at the oversampling clock frequency (e.g., 256 times the sample data rate, or about 11 MHz). This clock is conventionally generated by a phase-locked loop (PLL), based upon a system clock within the wireless telephone itself. As known in the art, phase locked-loop (PLL) circuits are used to generate stable clock signals at a fixed frequency relationship, generally a ratio of integers, relative to a reference clock. The frequency relationship is effected by a frequency divider applied to the reference clock and in the PLL feedback loop. In wireless telephones, the reference clock is typically the wireless clock frequency for the particular wireless transmission mode.
Modern advanced mobile computing devices and wireless telephone handsets are evolving from the so-called second generation (2G) technologies for wireless communications toward the capability of providing the so-called third generation (3G) wireless services. These 3G services are expected to extend current second generation voice and data services, and to include new very high bandwidth entertainment services including video and CD quality audio, interactive messaging including video and graphics, videoconferencing, video streaming, and remote control and monitoring services. These high-bandwidth services and applications of course place significant pressure on the wireless hardware, especially in receiving and outputting this multimedia content.
The digital signals from these various sources and transmission modes are at a wide range of data rates and frequencies. For example, digital audio tape (DAT) operates at a 48 kHz data rate, while compact disk (CD) audio is at a 44.1 kHz data rate. Other commonly encountered digital data rates include 32 kHz, 24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz. The advanced multi-purpose wireless telephone must therefore be able to perform digital-to-analog conversion of the incoming digital signals from each of these multiple signal sources, at each of these digital data rates, to provide a high-fidelity analog stereo audio output. However, the ability to convert data from any and all of these available data rates greatly complicates the architecture of the sigma-delta DAC.
By way of further explanation,
FIG. 1
illustrates a conventional arrangement of a sigma-delta DAC using a PLL-based clock. Incoming baseband digital signal S, having a bandwidth f
bw
, is sampled by latch
4
, which is clocked at an oversampling frequency f
S
applied by clock signal OSCLK from phase-locked loop (PLL)
2
. Oversampling frequency f
S
is a frequency that is generally a large integral multiple of the signal bandwidth f
bw
. While the Nyquist criterion requires sampling of a signal at twice its bandwidth in order to accurately recover the signal, oversampling frequency f
S
is typically much greater than twice the bandwidth f
bw
. For example, a typical oversampling multiple is 256. In the case of a signal bandwidth f
bw
of about 40 kHz, the oversampling frequency f
S
is on the order of 10 MHz or higher.
PLL
2
is constructed in the conventional manner, and as such includes input frequency divider
10
for generating a reference clock signal based upon wireless clock WCLK. Frequency divider
10
presents the reference clock to one input of phase detector
12
, which receives a feedback signal at its other input. Phase detector
12
produces an analog output signal based on the difference in phase between the reference clock and the feedback signal. This phase difference signal is filtered for stability by low-pass filter
14
, and is applied to the control input of voltage controlled oscillator (VCO)
16
. VCO
16
produces the output oversampling clock OSCLK, which is fed back through frequency divider
18
to the second input of phase detector
12
. The oversampling clock OSCLK is thus locked to wireless clock WCLK, at a frequency multiple determined by the divisor ratio of frequency dividers
18
,
10
.
The oversampling clock OSCLK is applied to sampling latch
4
, as noted above. Oversampling clock OSCLK also controls the modulation of sigma-delta modulator
6
, which modulates the m bits of the sampled input signal S to a single-bit signal, in this example. 1-bit DAC
8
, which is also clocked by oversampling clock OSCLK, receives the modulated output from modulator
6
, and produces output analog signal s(t).
While the arrangement of
FIG. 1
is well suited for generating an oversampling clock OSCLK at a reasonable multiple of wireless clock WCLK, this task becomes exceedingly difficult if signals of varying frequency are to be processed by this circuit. This is because there is no small set of integers that can be used in PLL
2
to produce the desired oversampling clock OSCLK at all of the necessary audio standard frequencies.
In addition to the differences in data rates of the various signal sources, multiple broadband communications standards are now in place. Indeed, the 3G communications standard itself (“IMT-2000”) defines a family of radio interfaces that are suitable for a wide range of environments. Furthermore, some wireless communications standards are extensions of 2G modulation techniques, extending the data rates of 2G standards toward the levels required for 3G communications. To further complicate this field, different regions of the world have gravitated toward different wireless communications technologies. Unfortunately, these various standards operate at different clock rates. For example, the wireless clock (WCLK in
FIG. 1
) for EDGE transmission is 26 MHz, the GSM clock is 13 MHz, the WCDMA clock is at 15.36 MHz, D-AMPS operates at 19.44 MHz, PDC operates at one of 12.6/12.8/14.4/16.8 MHz, PHS at 16.8 or 8.4 MHz, and AMPS operates at 14.4/15.36/16.8 MHz.
Because of the varying incoming signal sample rates and the wide number of possible wireless transmission modes, a set of ratios of relatively small integers of the various wireless- clock frequencies cannot be derived, for use in a conventional PLL, to produce the wide range of oversampling clock frequencies necessary for D/A conversion in all combinations.
By way of further background, another type of known oversampled DAC does not require the generation of clock frequencies at an exact multiple of the input sample rate. An example of a DAC of this type is illustrated in
FIG. 2
, in which digital signal S is sampled by latch
4
, oversampled by latch
5
, modulated by sigma-delta modulator
6
, an
Brady III Wade James
Neerings Ronald O.
Nguyen John
Young Brian
LandOfFree
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