Flexible reset scheme supporting normal system operation, test a

Details Flexible reset scheme supporting normal system operation, test a Flexible reset scheme supporting normal system operation, test a

1994-05-04

1999-04-13

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327415, H03K 302

Patent

active

058941762

ABSTRACT:
A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.

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Fletcher; "An Engineer Approach to Digital Design", 1980, pp. 608-612.

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