Flexible RAM clock enable

Details Flexible RAM clock enable Flexible RAM clock enable

2008-07-08

2008-07-08

Mai, Son L (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189040, C365S189080, C365S230050, C365S233100, C326S038000, C326S039000

Reexamination Certificate

active

07397726

ABSTRACT:
A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.

REFERENCES:
patent: 6097211 (2000-08-01), Couts-Martin et al.
patent: 6816979 (2004-11-01), Chen et al.
patent: 6950911 (2005-09-01), Cohen et al.
patent: 6992947 (2006-01-01), Pan et al.
patent: 7286415 (2007-10-01), Kwon
patent: 2006/0171239 (2006-08-01), Balasubramanian et al.
patent: 2007/0258313 (2007-11-01), Yu et al.

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