Flexible network processor scheduler and data flow

Details Flexible network processor scheduler and data flow Flexible network processor scheduler and data flow

2011-08-09

2011-08-09

Ryman, Daniel J (Department: 2466)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S392000, C370S428000

Reexamination Certificate

active

07995472

ABSTRACT:
A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

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