Flexible encoding method and architecture for high speed data tr

Details Flexible encoding method and architecture for high speed data tr Flexible encoding method and architecture for high speed data tr

1992-02-19

1993-09-14

Hoff, Marc S.

Coded data generation or conversion

Digital code to digital code converters

Byte length changed

341106, H03M 700

Patent

active

052453391

ABSTRACT:
In data transmission and storage using encoding through finite-state machines, the feedback link that updates each finite-state machine after each encoding step presents a bottleneck for a high speed implementation. The invention solves this problem for a class of finite-state machines that includes the encoder for the known 8B/10B Widmer-Franaszek code. The architecture consists of parallel finite-state units that are pipelined to run at a relatively low clock frequency. State updating is broken down into a feedforward part and a feedback part. In the feedback part, the state of each unit can be updated with a single operation. This allows efficient implementation of the finite-state encoder for practically any data rate just by appropriate pipelining and parallel processing.

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Int. Journal of Electronics, vol. 27, No. 5, Sep. 1983, pp. 440-451.
IEEE Trans. on Circuits & Systems, vol. 38, No. 5, May 1991, pp. 465-475.
IBM Journal of Res. & Dev., vol. 27, No. 5, Sep. 1983, pp. 440-451.

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